[Apologies if you receive multiple copies of this CFP]

IA^3 2017 Seventh Workshop on Irregular Applications: Architectures and Algorithms http://hpc.pnl.gov/IA3/ Monday, November 13, 2017 Colorado Convention Center Room 507 Denver, CO

In conjunction with SC17 In collaboration with SIGHPC Sponsored by TCHPC

Theme

Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, tables, sparse matrices, deep nets, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years.

This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms.

Program

9:00 - 9:10 Welcome and Introduction Antonino Tumeo, John Feo, Vito Giovanni Castellana

9:10 - 9:50 Keynote 1 - Chair: John Feo (PNNL) A Taxonomy of HPDA Algorithms programming of Irregular Algorithms Steve Conway (Hyperion Research)

9:50 - 10:00 Session 1: Parallel Algorithms Chair: Marco Minutoli (PNNL & WSU) Accelerating Energy Games Solvers on Modern Architectures Andrea Formisano, Raffaella Gentilini and Flavio Vella

10:00 - 10:30 Coffee Break

10:30 - 11:30 Session 2: Load Balancing Chair: TBD 10:30 - 10:55 Overcoming Load Imbalance for Irregular Sparse Matrices Goran Flegar and Hartwig Anzt 10:55 - 11:20 Progressive load balancing of asynchronous algorithms Justs Zarins and Michele Weiland 11:20 - 11:30 Enabling Work-Efficiency for High Performance Vertex-Centric Graph Analytics on GPUs Farzad Khorasani, Keval Vora, Rajiv Gupta and Laxmi N. Bhuyan

11:30 - 12:30 Session 3: Parallel Irregular Algorithms Chair: TBD 11:30 - 11:55 Parallel Depth-First Search for Directed Acyclic Graphs Maxim Naumov, Alysson Vrielink and Michael Garland 11:55 - 12:20 Optimizing Word2Vec Performance on Multicore Systems Vasudevan Rengasamy, Tao-Yang Fu, Wang-Chien Lee and Kamesh Madduri 12:20 -12:30 Spherical Region Queries on Multicore Architectures Hao Lu, Sudip Seal, Wei Guo and Jonathan Poplawsky

12:30 - 2:00 Lunch Break (on your own)

2:00 - 2:50 Keynote 2 - Chair: Vito Giovanni Castellana (PNNL) Quantum Computing and Irregular Applications Prof. Fred Chong (University of Chicago)

2:50 - 3:00 Session 4: Data Layouts Chair: Marco Minutoli (PNNL & WSU) An Efficient Data Layout Transformation Algorithm for Locality-Aware Parallel Sparse FFT Cheng Wang, Sunita Chandrasekaran and Barbara Chapman

3:00 - 3:30 Coffee Break

3:30 - 4:30 Session 5: Architecture for Irregular Applications Chair: TBD 3:30 - 3:55 A Case for Migrating Execution for Irregular Applications Peter Kogge and Shannon Kuntz 3:55 - 4:20 Pressure-Driven Hardware Managed Thread Concurrency for Irregular Applications John Leidel, Xi Wang and Yong Chen 4:20 - 4:30 Evaluation of Knight Landing High Bandwidth Memory for HPC Workloads Solmaz Salehian and Yonghong Yan

4:30 - 5:30 Debate - Moderator: Ruud Van Der Pas (Oracle) Proposition: “Specialized, perhaps configurable, hardware and software are necessary to achieve high-performance, scalable data analytics" Panelists: Rich Vuduc (Georgia Tech), Franz Franchetti (CMU), Eric Van Hensbergen (ARM), David Wang (Samsung)