``` ***************************************************************************
CALL FOR PARTICIPATION
2nd Workshop on Hierarchical Parallelism for Exascale Computing ---HiPar21--- Sunday, Nov. 14th
Held in conjunction with SC21, Nov. 14-19 2021, St. Louis, USA In cooperation with: IEEE and TCHPC.
www.hipar.net
***************************************************************************
================================ Summary ================================ High Performance Computing (HPC) platforms are evolving towards having fewer but more powerful nodes, driven by the increasing number of physical cores in multiple sockets and accelerators. The boundary between nodes and networks is starting to blur, with some nodes now containing tens of compute elements and memory sub-systems connected via a memory fabric. The immediate consequence is an increase in complexity due to ever more complex architectures (e.g., memory hierarchies), novel accelerator designs, and energy constraints. Spurred largely by this trend, hierarchical parallelism is gaining momentum. This approach embraces, rather than avoiding, the intrinsic complexity of current and future HPC systems by exploiting parallelism at all levels: compute, memory and network. This workshop focuses on hierarchical parallelism. It aims to bring together application, hardware, and software practitioners proposing new strategies to fully exploit computational hierarchies, and examples to illustrate their benefits to achieve extreme scale parallelism.
================================ Scope and Aims ================================ HiPar21 welcomes HPC practitioners from all areas, ranging from hardware and compiler experts to algorithms and software developers, to present and discuss new studies, approaches, and cutting-edge ideas to utilize multi-level parallelism for extreme scale computing.
We welcome contributions from the HPC community addressing the use of emerging architectures, focusing particularly on those characterized by fewer but more powerful nodes as well as systems with hierarchical network with tiered communication semantics. Specifically, the emphasis is on the design, implementation, and application of programming models for multi-level parallelism, including abstractions for hierarchical memory access, heterogeneity, multi-threading, vectorization, and energy efficiency, as well as scalability and performance studies thereof.
Of particular interest are models addressing these concerns portably: providing ease of programming and maintaining performance in the presence of varied accelerators, hardware configurations, and execution models. Studies that explore the merits of specific approaches to addressing these concerns, such as generic programming or domain specific languages, are also in scope. The workshop is not limited to the traditional HPC software community. As one example, another key topic is the use of hierarchical parallelism in dealing with the challenges arising in machine learning due to the growing importance of this field, the large scale of systems tackled in that area, and the increasing interest from more traditional HPC areas.
Finally, we remark that a key goal of HiPar21 is to highlight not just success stories. We welcome contributions that provide compelling results and discussions on the hardest challenges to overcome leading to exascale, the role hierarchical parallelism can play in them, as well as relevant drawbacks.
================================ Topics ================================ Submissions are encouraged in, but not limited to the following areas:
* Hardware, software, and algorithmic advances for efficient use of memory hierarchies, multi-threading and vectorization; * Efficient use of nested parallelism, for example CUDA dynamic parallelism, for large scale simulations; * Hierarchical work scheduling and execution; * Programming heterogeneous nodes; * Leading-edge programming models, for example fully distributed task-based models and hybrid MPI+X, with X representing shared memory parallelism via threads, vectorization, tasking or parallel loop constructs. * Implementations of algorithms that are natural fits for nested work (for example approaches that use recursion); * Challenges and successes in managing computing hierarchies; * Examples demonstrating effective use of the combination of inter-node and intra-node parallelism; * Novel approaches leveraging asynchronous execution to maximize efficiency; * Challenges and successes of porting of existing applications to many-core and heterogeneous platforms; * Recent developments in compiler optimizations for emerging architectures; * Applications of hierarchical programming models from emerging AI fields, for example deep learning and extreme-scale data analytics.
================================ Papers Submission Guidelines ================================ We solicit papers submissions in the following categories: (a) Regular research papers: Intended for submissions describing original work and ideas that have NOT appeared in another conference or journal, and are NOT currently under review for any other conference or journal. Regular papers must be at least (6) and must not exceed (10) letter size pages (U.S. letter – 8.5"x11"). Accepted regular papers will be published in the workshop proceedings in cooperation with IEEE TCHPC.
(b) Short papers: Intended for material that is not mature enough for a full paper, to present novel, interesting ideas or preliminary results that will be formally submitted elsewhere. Short papers must not exceed four (4) pages. Short papers will NOT be included in the proceedings.
Please note that: - The page limits above only apply to the core text, content-related appendices, and figures. References and reproducibility appendix do not count against the page limit.
- When deciding between submissions with comparable evaluations, priority will be given to those with higher quality of presentation and whose focus relates more directly to the workshop themes.
- Papers and must be submitted electronically at https://submissions.supercomputing.org/ and must follow the IEEE format: www.ieee.org/conferences/publishing/templates.html
==================================================== !!New concept!!: Algorithm Brainstorming Session ==================================================== Are you working on code/algorithms and would like to see if and how it can benefit from a hierarchical approach? Or exploring state-of-the-art hierarchical approaches and leading edge programming models and desire feedback about how to approach such problems in practice? This new idea we are proposing might be of interest to you!
We invite practitioners at all levels (especially encouraging participation from junior scholars) to submit a one-page summary describing an algorithm of their interest that is NOT already exploiting hierarchical parallelism and they would like to improve/change. We will select a subset of these submissions and, on the workshop day, we will host parallel breakout sessions moderated by experts in the field, to guide the brainstorming discussions on if/how one can exploit hierarchical parallelism to improve them.
The submission must be 1 page and should address (at a high-level) these sections: motivation/application, core algorithm, desired scale of execution, and current bottlenecks (if any). The single page limit only applies to the core text: figures, references, and appendices do not count against the page limit.
Please note that: - We will prioritize submissions by junior people. We believe this would be most beneficial as a way of allowing more experienced engineers and researchers to share their experience and approaches to solving this sort of problem.
- We expect each submission to present code/algorithms that are relevant to the person/group submitting it. For example, if you are a researcher working on CFD, we expect your submission to be related to *your* code and computational issues, not on a different group's or commercial code.
- We envision holding two or three parallel sessions. Each session will be approximately 45/60 mins: 10/15 mins for the author to present the algorithm and motivation, followed by the discussion until the time ends. However, we reserve to expand the number of sessions if we receive a substantial number of submissions/interest.
================================ Reproducibility Initiative ================================ HiPar21 follows the SC21 reproducibility and transparency initiative. The SC21 details can be found at: https://sc21.supercomputing.org/submit/reproducibility-initiative.
HiPar21 requires all submission to include an Artifact Description (AD) Appendix. Note that the AD will be auto-generated from the author's responses to a form embedded in the online submission system. The Artifact Evaluation (AE) remains optional. We also encourage authors to follow the transparency initiative for two reasons: (a) it helps the authors themselves with the actual writing and structuring of the paper to express the research process; (b) it helps reviewers and readers to understand the thinking process used by the authors to plan, obtain and explain their results.
================================ Important dates ================================ Submission Deadline: August 30th, 2021 (AoE) Author Notification: September 13, 2021 Camera Ready: October 4, 2021 Final Program: October 9, 2021 Workshop Date: Sunday, Nov. 14th
Note that SC21 is currently planning to host the conference in person, but to also include a virtual platform to support remote attendance and to enhance the in-person activities. However, at this time the virtual platform support is still unknown, and we want to explicitly state that there is always the possibility of SC21 becoming fully virtual. Therefore, please refer to the our workshop and SC21 websites for the latest information.
================================ Chairs and Committees ================================ Workshop chair: - Francesco Rizzi NexGen Analytics
Organizing Committee: - Daisy Hollman Google - Lee Howes Facebook - Xiaoye Sherry Li Lawrence Berkeley National Lab
Program Committee Chairs: - Christian Trott Sandia National Labs - Filippo Spiga NVIDIA
Program Committee: - Mark Bull EPCC - Irina Demeshko LANL - Marta Garcia Gasulla BSC - Anja Gerbes TU Dresden - Mark Hoemmen Stellar Science - Toshiyuki Imamura RIKEN - Guido Juckeland Helmholtz Center - Hartmut Kaiser LSU - Vivek Kale Brookhaven Labs - Jonathan Lifflander Sandia National Labs - James Lin Shanghai J.Tong Univ. - Nicholas Malaya AMD - Aram Markosyan Xilinx - Rui Oliveira INESC TEC - Philippe Pebay NexGen Analytics - Zhiqi Tao Intel - Flavio Vella Univ. of Bozen - Michèle Weiland EPCC - Jeremiah Wilke Google
================================ Contact information: ================================ For questions, please email us at: hiparws@gmail.com ```
``` ***************************************************************************
CALL FOR PARTICIPATION [extended deadline]
2nd Workshop on Hierarchical Parallelism for Exascale Computing ---HiPar21--- Sunday, Nov. 14th
Held in conjunction with SC21, Nov. 14-19 2021, St. Louis, USA In cooperation with: IEEE and TCHPC.
www.hipar.net
***************************************************************************
================================ Summary ================================ High Performance Computing (HPC) platforms are evolving towards having fewer but more powerful nodes, driven by the increasing number of physical cores in multiple sockets and accelerators. The boundary between nodes and networks is starting to blur, with some nodes now containing tens of compute elements and memory sub-systems connected via a memory fabric. The immediate consequence is an increase in complexity due to ever more complex architectures (e.g., memory hierarchies), novel accelerator designs, and energy constraints. Spurred largely by this trend, hierarchical parallelism is gaining momentum. This approach embraces, rather than avoiding, the intrinsic complexity of current and future HPC systems by exploiting parallelism at all levels: compute, memory and network. This workshop focuses on hierarchical parallelism. It aims to bring together application, hardware, and software practitioners proposing new strategies to fully exploit computational hierarchies, and examples to illustrate their benefits to achieve extreme scale parallelism.
================================ Scope and Aims ================================ HiPar21 welcomes HPC practitioners from all areas, ranging from hardware and compiler experts to algorithms and software developers, to present and discuss new studies, approaches, and cutting-edge ideas to utilize multi-level parallelism for extreme scale computing.
We welcome contributions from the HPC community addressing the use of emerging architectures, focusing particularly on those characterized by fewer but more powerful nodes as well as systems with hierarchical network with tiered communication semantics. Specifically, the emphasis is on the design, implementation, and application of programming models for multi-level parallelism, including abstractions for hierarchical memory access, heterogeneity, multi-threading, vectorization, and energy efficiency, as well as scalability and performance studies thereof.
Of particular interest are models addressing these concerns portably: providing ease of programming and maintaining performance in the presence of varied accelerators, hardware configurations, and execution models. Studies that explore the merits of specific approaches to addressing these concerns, such as generic programming or domain specific languages, are also in scope. The workshop is not limited to the traditional HPC software community. As one example, another key topic is the use of hierarchical parallelism in dealing with the challenges arising in machine learning due to the growing importance of this field, the large scale of systems tackled in that area, and the increasing interest from more traditional HPC areas.
Finally, we remark that a key goal of HiPar21 is to highlight not just success stories. We welcome contributions that provide compelling results and discussions on the hardest challenges to overcome leading to exascale, the role hierarchical parallelism can play in them, as well as relevant drawbacks.
================================ Topics ================================ Submissions are encouraged in, but not limited to the following areas:
* Hardware, software, and algorithmic advances for efficient use of memory hierarchies, multi-threading and vectorization; * Efficient use of nested parallelism, for example CUDA dynamic parallelism, for large scale simulations; * Hierarchical work scheduling and execution; * Programming heterogeneous nodes; * Leading-edge programming models, for example fully distributed task-based models and hybrid MPI+X, with X representing shared memory parallelism via threads, vectorization, tasking or parallel loop constructs. * Implementations of algorithms that are natural fits for nested work (for example approaches that use recursion); * Challenges and successes in managing computing hierarchies; * Examples demonstrating effective use of the combination of inter-node and intra-node parallelism; * Novel approaches leveraging asynchronous execution to maximize efficiency; * Challenges and successes of porting of existing applications to many-core and heterogeneous platforms; * Recent developments in compiler optimizations for emerging architectures; * Applications of hierarchical programming models from emerging AI fields, for example deep learning and extreme-scale data analytics.
================================ Papers Submission Guidelines ================================ We solicit papers submissions in the following categories: (a) Regular research papers: Intended for submissions describing original work and ideas that have NOT appeared in another conference or journal, and are NOT currently under review for any other conference or journal. Regular papers must be at least (6) and must not exceed (10) letter size pages (U.S. letter – 8.5"x11"). Accepted regular papers will be published in the workshop proceedings in cooperation with IEEE TCHPC.
(b) Short papers: Intended for material that is not mature enough for a full paper, to present novel, interesting ideas or preliminary results that will be formally submitted elsewhere. Short papers must not exceed four (4) pages. Short papers will NOT be included in the proceedings.
Please note that: - The page limits above only apply to the core text, content-related appendices, and figures. References and reproducibility appendix do not count against the page limit.
- When deciding between submissions with comparable evaluations, priority will be given to those with higher quality of presentation and whose focus relates more directly to the workshop themes.
- Papers and must be submitted electronically at https://submissions.supercomputing.org/ and must follow the IEEE format: www.ieee.org/conferences/publishing/templates.html
==================================================== Algorithm Brainstorming Session ==================================================== Are you working on code/algorithms and would like to see if and how it can benefit from a hierarchical approach? Or exploring state-of-the-art hierarchical approaches and leading edge programming models and desire feedback about how to approach such problems in practice? This new idea we are proposing might be of interest to you!
We invite practitioners at all levels (especially encouraging participation from junior scholars) to submit a one-page summary describing an algorithm of their interest that is NOT already exploiting hierarchical parallelism and they would like to improve/change. We will select a subset of these submissions and, on the workshop day, we will host parallel breakout sessions moderated by experts in the field, to guide the brainstorming discussions on if/how one can exploit hierarchical parallelism to improve them.
The submission must be 1 page and should address (at a high-level) these sections: motivation/application, core algorithm, desired scale of execution, and current bottlenecks (if any). The single page limit only applies to the core text: figures, references, and appendices do not count against the page limit.
Please note that: - We will prioritize submissions by junior people. We believe this would be most beneficial as a way of allowing more experienced engineers and researchers to share their experience and approaches to solving this sort of problem.
- We expect each submission to present code/algorithms that are relevant to the person/group submitting it. For example, if you are a researcher working on CFD, we expect your submission to be related to *your* code and computational issues, not on a different group's or commercial code.
- We envision holding two or three parallel sessions. Each session will be approximately 45/60 mins: 10/15 mins for the author to present the algorithm and motivation, followed by the discussion until the time ends. However, we reserve to expand the number of sessions if we receive a substantial number of submissions/interest.
================================ Reproducibility Initiative ================================ HiPar21 follows the SC21 reproducibility and transparency initiative. The SC21 details can be found at: https://sc21.supercomputing.org/submit/reproducibility-initiative.
HiPar21 requires all submission to include an Artifact Description (AD) Appendix. Note that the AD will be auto-generated from the author's responses to a form embedded in the online submission system. The Artifact Evaluation (AE) remains optional. We also encourage authors to follow the transparency initiative for two reasons: (a) it helps the authors themselves with the actual writing and structuring of the paper to express the research process; (b) it helps reviewers and readers to understand the thinking process used by the authors to plan, obtain and explain their results.
================================ Important dates ================================ Submission Deadline (extended): September 8th, 2021 (AoE) Author Notification: September 22, 2021 Camera Ready: October 4, 2021 Final Program: October 9, 2021 Workshop Date: Sunday, Nov. 14th
Note that SC21 is currently planning to host the conference in person, but to also include a virtual platform to support remote attendance and to enhance the in-person activities. However, at this time the virtual platform support is still unknown, and we want to explicitly state that there is always the possibility of SC21 becoming fully virtual. Therefore, please refer to our workshop and SC21 websites for the latest information.
================================ Chairs and Committees ================================ Workshop chair: - Francesco Rizzi NexGen Analytics
Organizing Committee: - Daisy Hollman Google - Lee Howes Facebook - Xiaoye Sherry Li Lawrence Berkeley National Lab
Program Committee Chairs: - Christian Trott Sandia National Labs - Filippo Spiga NVIDIA
Program Committee: - Mark Bull EPCC - Irina Demeshko LANL - Marta Garcia Gasulla BSC - Anja Gerbes TU Dresden - Mark Hoemmen Stellar Science - Toshiyuki Imamura RIKEN - Guido Juckeland Helmholtz Center - Hartmut Kaiser LSU - Vivek Kale Brookhaven Labs - Jonathan Lifflander Sandia National Labs - James Lin Shanghai J.Tong Univ. - Nicholas Malaya AMD - Aram Markosyan Facebook - Rui Oliveira INESC TEC - Philippe Pebay NexGen Analytics - Zhiqi Tao Intel - Flavio Vella Univ. of Bozen - Michèle Weiland EPCC - Jeremiah Wilke Google
================================ Contact information: ================================ For questions, please email us at: hiparws@gmail.com ```
computational.science@lists.iccsa.org
-
Francesco Rizzi