---------------------------------------------------------------------------------------- Please accept our apologies if you have received multiple copies. ----------------------------------------------------------------------------------------- Deadline Extension
-------------------- REV-A 2017 CFP --------------------- Re-Emergence of Vector Architectures Workshop - https://rev-a.github.io/
To be held in Conjunction with the IEEE Cluster 2017 September 5, 2017, Honolulu, Hawaii, USA
Paper submission: REV-A Submissionhttps://easychair.org/conferences/overview.cgi?a=13663824 Papers due: June 25, 2017
The commoditization of high performance computing to a broader range of applications coupled with the reduction in performance improvement from traditional scaling technologies has led to a broad interest in a number of new compute acceleration technologies from GPGPUs to CGRAs and FPGAs. Meanwhile, SIMD widths have been widening to try to keep up with computational demand and general purpose architectures have started incorporating features from the vector architectures that used to dominate high performance computing. From IBM's Vector Media eXtension (VMX) to NEC's SX architecture to Intel's Advanced Vector eXtension (AVX) to ARM's recently announced Scalable Vector Extension (SVE) -- all of the major general purpose architectures seem to have embraced a return to vector based functionality.
Supporting these hardware developments there are a number of features being proposed for incorporation into modern programming models and languages in order to support the vector additions as well as restructuring memory access in order to feed the computational pipelines. Meanwhile application developers have been hard at work trying to refactor code to take advantage of wider vector units and more complicated memory hierarchies. Tools and techniques for developing for these new vector architectures are still evolving, particularly on emerging languages and runtimes.
The REV-A 2017 workshop will be a full-day meeting to be held at the IEEE Cluster 2017, in Honolulu, Hawaii, focusing on all aspects of vector architectures, programming models, programming frameworks, and applications. Topics of interest, of both theoretical and practical significance, include but are not limited to:
* Programming framework * Programming model and language explorations * Compilation and optimization including: o algorithmic improvements o code optimization * Performance Analysis and Debugging Tools * Performance Metrics and Evaluations * Libraries and run-time systems * Design, generation, verification and validation of representative applications * Case-studies of representative applications * Innovative applications for vector architectures * Hardware studies and micro-architectural implementation tradeoffs
The REV-A workshop proceedings will be published along with the IEEE Cluster Digital Library. Submitted manuscripts should follow the IEEE Xplore format for publication: not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages, including figures, tables, and references. Manuscripts must be submitted electronically in PDF format. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers may not have appeared in or be under consideration for another workshop, conference, or journal. Accepted papers will have a page limit of 8 pages, and authors can purchase an additional 2 pages, for a total of 10 pages maximum.
Important Dates: Papers due: June 25, 2017 <<<--- Extension Author notification: July 17, 2017 Camera-ready final papers due: July 30, 2017 REV-A Workshop: September 05, 2017
Workshop Chairs: Luiz DeRose Cray Inc. Eric Van Hensbergen ARM Research
Program Committee: David Abramson University of Queensland Bronis R. de Supinski Lawrence Livermore National Laboratory Mootaz N. Elnozahy KAUST Roger Espasa SemiDynamics Michael Garland NVIDIA Ian Karlin Lawrence Livermore National Laboratory David Lilja University of Minnesota Sally McKee Chalmers University of Technology Sanyam Mehta Cray Inc. Hiroshi Nakashima Kyoto University Lawrence Rauchwerger Texas A&M University Mitsuhisa Sato Riken Sunil Shrestha Cray Inc. Xinmin Tian Intel Mateo Valero Barcelona Supercomputing Center / UPC Jeffrey Vetter Oak Ridge National Laboratory Felix Wolf TU Darmstadt Pen-Chung Yew University of Minnesota