11th of September, Bristol University, UK.
Part of the Marionet UK Many-core Research Network
This 1-day workshop includes invited presentations from industry and academia investigating how issues of performance and power have resulted in significant efforts done in new accelerator hardware designs and new ways to use available hardware originally not designed for HPC. Examples include novel use of embedded multi-core CPUs and hardware accelerators based on GPUs and FPGAs. Domain specific CPU architectures capable of delivering performance and ease of programmability are also the focus of intensive research and development together with innovative programming models and algorithms exploiting HPC hardware or software. The demand of techniques to handle the debugging and optimization of these systems are also increasing as the human capability of understanding complex software/hardware interactions reaches its limit.
CALL FOR PARTICIPATION
https://seis.bristol.ac.uk/~eejlny/nghpc/eehco.htmhttps://fpl2018.org/
*************************************************************************** Registration Link (free, includes refreshments and lunch)
https://www.eventbrite.com/e/workshop-on-next-generation-hardware-for-high-p...https://fpl2018.org/registration/
Workshop program is available at:
https://seis.bristol.ac.uk/~eejlny/nghpc/program.htm
Thanks,
Jose Nunez-Yanez