computational.science

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[CFP] IA^3 2020 - NEW DEADLINE SEPTEMBER 10th
by Tumeo, Antonino 29 Aug '20

29 Aug '20

[Please accept our apologies if you receive multiple copies of this message.] !!!!!!!!! NEWS: DEADLINE EXTENDED TO SEPTEMBER 10th !!!!!!!! IA^3 2020 10th Workshop on Irregular Applications: Architectures and Algorithms http://hpc.pnl.gov/IA3 November 11, 2020 Virtual Workshop In conjunction with SC20 Sponsored by IEEE TCHPC -------------------- Call for Papers -------------------- Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers. Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Emerging supercomputing applications are moving towards a convergence of scientific simulation, data analytics, and learning algorithms, mixed in various ways. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years. This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to: - Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors - Network architectures and interconnect (including high-radix networks, optical interconnects) - Novel memory architectures and designs (including processors-in memory) - Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) - Modeling, simulation and evaluation of novel architectures with irregular workloads - Innovative algorithmic techniques - Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.) - Impact of irregularity on machine learning approaches - Parallelization techniques and data structures for irregular workloads - Data structures combining regular and irregular computations (e.g., attributed graphs) - Approaches for managing massive unstructured datasets (including streaming data) - Languages and programming models for irregular workloads - Library and runtime support for irregular workloads - Compiler and analysis techniques for irregular workloads - High performance data analytics applications (including graph databases and solutions that combine graph algorithms with machine learning) - Applications that integrate scientific simulation, data analytics, and learning, and require efficient execution of irregular workloads Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation. -------------------- Important Dates -------------------- Abstract Submission: September 10, 2020 (AoE) Position or Regular Paper Submission: September 10, 2020 (AoE) Notification: September 28, 2020 Artifact Evaluation: September 28, 2020 - October 10, 2020 Camera-ready: October 10, 2020 Workshop: November 11, 2020 -------------------- Submissions -------------------- Submission site: https://submissions.supercomputing.org Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers (excluding references). Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix. The templates are available at: http://www.ieee.org/conferences_events/conferences/publishing/templates.html. Accepted papers will be published in the IEEE Digital Library through IEEE TCHPC. -------------------- Artifact Description & Evaluation -------------------- This edition of the workshop invites authors of regular papers to follow a reproducibility initiative like the main SC Conference, with specific appendices for the Artifact Description (AD) and the Artifact Evaluation (AE). Please refer to the SC reproducibility page for further details on the rationale behind AD and AE: https://sc20.supercomputing.org/submit/transparency-reproducibility-initiat… Authors of regular papers will be able to use up to one (1) additional page to provide an Artifact Description (AD) Appendix, describing the details of their software environments and computational experiments to the extent that an independent person could replicate their results. Note that differently from the main conferene, this additional page is voluntary (not mandatory - i.e., if a paper has no computational results, do not attach it) for the workshop, and must focus only on details on software environments and methods to execute the experiments. It should not add details on the proposed technical approaches. Additionally, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation (AE) process. The process is voluntary, but authors that will participate in the AE will be eligible for the Best Paper Award of the workshop. Supporting materials for the AE include access to the actual software artifact, shared publicly (for example, through the CK - Collective Knowledge - https://github.com/ctuning/ck format), and two (2) further additional pages of the paper that details how to reproduce the results of the paper. For details on how to submit supporting materials to the AE process, please refer to: http://ctuning.org/ae/submission.html. Authors participating in the AE will receive an assessment of the artifact, and the related badge on their paper. For any additional question on the AD and the AE please contact the Artifact Evaluation Chair, Biagio Cosenza, at bcosenza(a)unisa.it. -------------------- Special Issue -------------------- Authors of papers accepted to the workshop will also be invited to submit extended version of their papers to a Special Issue of the journal of Parallel Computing (ParCO) on Hardware/Software Co-design for Sparse and Irregular Applications. Submissions for the special issue with open December 1, 2020 and will close on March 1, 2021. For more information on this special issue, please visit the special issue page and/or contact the guest co-editors, Flavio Vella (flavio.vella(a)unibz.it) and Antonino Tumeo (antonino.tumeo(a)pnnl.gov). https://www.journals.elsevier.com/parallel-computing/call-for-papers/hardwa… -------------------- Organizers -------------------- Antonino Tumeo (PNNL), antonino.tumeo(a)pnnl.gov John Feo (PNNL), john.feo(a)pnnl.gov Vito Giovanni Castellana (PNNL), vitoGiovanni.castellana(a)pnnl.gov -------------------- Proceedings Chair -------------------- Marco Minutoli (PNNL and WSU), marco.minutoli(a)pnnl.gov -------------------- Artifact Evaluation Chair -------------------- Biagio Cosenza (University of Salerno), bcosenza(a)unisa.it -------------------- Technical Program Committee -------------------- Nesreen Ahmed, Intel, US Johnathan Alsop, AMD, US Eishi Arima, University of Tokyo, JP Scott Beamer, University of California, Santa Cruz, US Jonathan Beard, ARM, US Michela Becchi, North Carolina State University, US Sanjukta Bhowmick, University of North Texas, US Erik Boman, SNL, US David Brooks, Harvard University, US Prerna Budhkar, Intel, US Aydin Buluc, LBNL, US Anastasiia Butko, LBNL, US Assefaw Gebremedhin, Washington State University, US Cat Graves, HPE, US Rajiv Gupta, University of California, Riverside, US Peter M. Kogge, Notre Dame University, US John Leidel, Tactical Computing Lab, US Kamesh Madduri, Pennsylvania State University José Moreira, IBM Research, US Miquel Moretó, Barçelona Supercomputing Center, ES Maxim Naumov, Facebook, US Fanny Nina-Paravecino, Microsoft, US Roger Pearce, LLNL, US Keshav Pingali, University of Texas, Austin, US Alejandro Rico, ARM, US Jason Riedy, Georgia Tech, US Thomas B. Rolinger, University of Maryland, US Kentaro Sano, RIKEN, JP John Shalf, LBNL, US Shaden Smith, Microsoft, US Tyler Sorensen, University of California, Santa Cruz, US Ruud van der Pas, Oracle, NL Ana Lucia Varbanescu, University of Amsterdam, NL Flavio Vella, Free University of Bozen, IT Other members TBD

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CFP HiPar20: submission deadline. extended to Sept. 7th
by Rizzi, Francesco NMN 28 Aug '20

28 Aug '20

--- Submission deadline extended to Sept. 7th --- ******************************************************************** Call for Participation Workshop on Hierarchical Parallelism for Exascale Computing ---HiPar20--- Held in conjunction with SC20 - virtual event In cooperation with: IEEE and TCHPC. www.hipar.net ******************************************************************** ================================ Summary ================================ High Performance Computing (HPC) platforms are evolving towards having fewer but more powerful nodes, driven by the increasing number of physical cores in multiple sockets and accelerators. The boundary between nodes and networks is starting to blur, with some nodes now containing tens of compute elements and memory sub-systems connected via a memory fabric. The immediate consequence is an increase in complexity due to ever more complex architectures (e.g., memory hierarchies), novel accelerator designs, and energy constraints. Spurred largely by this trend, hierarchical parallelism is gaining momentum. This approach embraces, rather than avoiding, the intrinsic complexity of current and future HPC systems by exploiting parallelism at all levels: compute, memory and network. This workshop focuses on hierarchical parallelism. It aims to bring together application, hardware, and software practitioners proposing new strategies to fully exploit computational hierarchies, and examples to illustrate their benefits to achieve extreme scale parallelism. ================================ Scope and Aims ================================ HiPar20 is designed to showcase new studies, approaches, and cutting-edge ideas on hierarchical parallelism for extreme-scale computing. We welcome papers and talks from the HPC community addressing the use of emerging architectures — focusing particularly on those characterized by fewer but more powerful nodes as well as systems with hierarchical network with tiered communication semantics. Specifically, the emphasis is on the design, implementation, and application of programming models for multi-level parallelism, including abstractions for hierarchical memory access, heterogeneity, multi-threading, vectorization, and energy efficiency, as well as scalability and performance studies thereof. Of particular interest are models addressing these concerns portably: providing ease of programming and maintaining performance in the presence of varied accelerators, hardware configurations, and execution models. Studies that explore the merits of specific approaches to addressing these concerns, such as generic programming or domain specific languages, are also in scope. The workshop is not limited to the traditional HPC software community. As one example, another key topic is the use of hierarchical parallelism in dealing with the challenges arising in machine learning due to the growing importance of this field, the large scale of systems tackled in that area, and the increasing interest from more traditional HPC areas. A goal of HiPar20 is to highlight not just success stories but also discuss drawbacks and challenges. HiPar20 welcomes HPC practitioners from all areas, ranging from hardware and compiler experts to algorithms and software developers, to present and discuss the state of the art in emerging approaches to utilize multi-level parallelism for extreme scale computing. ================================ Topics ================================ Submissions are encouraged in, but not limited to the following areas: * Hierarchical work scheduling and execution; * Hardware, software, and algorithmic advances for efficient use of memory hierarchies, multi-threading and vectorization; * Efficient use of nested parallelism, for example CUDA dynamic parallelism, for large scale simulations; * Programming heterogeneous nodes; * Leading-edge programming models, for example fully distributed task-based models and hybrid MPI+X, with X representing shared memory parallelism via threads, vectorization, tasking or parallel loop constructs. * Implementations of algorithms that are natural fits for nested work (for example approaches that use recursion); * Challenges and successes in managing computing hierarchies; * Examples demonstrating effective use of the combination of inter-node and intra-node parallelism; * Novel approaches leveraging asynchronous execution to maximize efficiency; * Challenges and successes of porting of existing applications to many-core and heterogeneous platforms; * Recent developments in compiler optimizations for emerging architectures; * Applications of hierarchical programming models from emerging AI fields, for example deep learning and extreme-scale data analytics. ================================ Submission Guidelines ================================ We solicit submissions in the following categories: (a) Regular research papers: Intended for submissions describing original work and ideas that have not appeared in another conference or journal, and are not currently under review for any other conference or journal. Regular papers must be at least (6) and must not exceed (10) letter size pages (U.S. letter – 8.5"x11"). Accepted regular papers will be published in the workshop proceedings in cooperation with IEEE TCHPC. (b) Short papers: Intended for material that is not mature enough for a full paper, to present novel, interesting ideas or preliminary results that will be formally submitted elsewhere. Short papers must not exceed four (4) pages. Short papers will NOT be included in the proceedings. Please note that: - The page limits above only apply to the core text, content-related appendices, and figures. References and reproducibility appendix do not count against the page limit. - When deciding between submissions with comparable evaluations, priority will be given to those with higher quality of presentation and whose focus relates more directly to the workshop themes. - Papers must be submitted electronically at https://submissions.supercomputing.org/ and must follow the IEEE format: www.ieee.org/conferences/publishing/templates.html ================================ Reproducibility Initiative ================================ HiPar20 follows the SC20 reproducibility and transparency initiative. The SC20 details can be found at: https://sc20.supercomputing.org/submit/transparency-reproducibility-initiat…. HiPar20 requires all submission to include an Artifact Description (AD) Appendix. Note that the AD will be auto-generated from author responses to a form embedded in the online submission system. The Artifact Evaluation (AE) remains optional. We also encourage authors to follow the transparency initiative for two reasons: (a) it helps the authors themselves with the actual writing and structuring of the paper to express the research process; (b) it helps readers understand the thinking process used by the authors to plan, obtain and explain their results. ================================ HiPar20 will be virtual ================================ SCC20 will be fully virtual: https://sc20.supercomputing.org/2020/07/27/sc20-virtual-event-announced-by-… Please refer to our website www.hipar.net for latest updates. ================================ Important dates ================================ Submission Deadline: September 7th, 2020 (AoE) Author Notification: September 23, 2020 Camera Ready: October 5, 2020 Final Program: October 9, 2020 Virtual Workshop Date: November 11, 2020 (10am-6.30pm EST) ================================ Chairs and Committees ================================ Workshop chair: - Francesco Rizzi NexGen Analytics Organizing Committee: - D.S. Hollman Sandia National Labs - Lee Howes Facebook - Xiaoye Sherry Li Lawrence Berkeley National Lab Program Committee Chairs: - Christian Trott Sandia National Labs - Filippo Spiga NVIDIA Program Committee: - Mark Bull EPCC - Carlo Cavazzoni CINECA - Benjamin Cumming CSCS - Chris Forster NVIDIA - Marta Garcia Gasulla BSC - Anja Gerbes Goethe Uni.Frankfurt - Mark Hoemmen Stellar Science - Toshiyuki Imamura RIKEN - Guido Juckeland Helmholtz Center - Hartmut Kaiser LSU - Vivek Kale Brookhaven Labs - Jonathan Lifflander Sandia National Labs - James Lin Shanghai J.Tong Univ. - Aram Markosyan Xilinx - Rui Oliveira INESC TEC - Philippe Pebay NexGen Analytics - Zhiqi Tao Intel - Flavio Vella Univ. of Bozen - Michèle Weiland EPCC - Jeremiah Wilke Sandia National Labs ================================ Contact information: ================================ For questions, please email us at: hiparws(a)gmail.com

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HPBench 2020 (10 days to deadline! )
by Samar Aseeri 27 Aug '20

27 Aug '20

Dear Sir, dear Madam, The event is going online this year. We accept papers, short papers, poster papers and posters (see below submission guidelines). There will be outstanding paper and poster awards as well. Please, can you pass this announcement also to interested colleagues. Kind regards ========================================================================== CALL FOR PAPERS The 7th Special Session on High Performance Computing for Application Benchmarking and Optimization (HPBench 2020) As part of the International Conference on High Performance Computing & Simulation (HPCS 2020) http://hpcs2020.cisedu.info/ or http://conf.cisedu.info/rp/hpcs20 Barcelona, Spain (Virtual/Online event) ========================================================================== Benchmarking is an essential aspect of modern high performance computing and computational science, and as such, it provides a means for quantifying and comparing the performance of different computer systems. With a large combination of aspects to benchmark, all the way from the capability of a single core, to cluster configuration, and to various software configurations, the benchmarking process is more of an art than science. However, the results of this process drive modern science and are vital for the community to draw sensible conclusions on the performance of applications and systems. This special session focuses on research work aimed at benchmarking modern parallel and distributed systems for addressing a number of real world problems. As such, contributions concerning the definition of new open platforms, new benchmarks to match modern architectural evolutions, studies on the aspects of benchmarking different aspects of systems (from raw runtime performance to energy consumption to energy consumed per data movement) and mathematical foundations of benchmarking are sought. IMPORTANT DATES : Papers Due: 07 September 2020 - Extended Author Notification: 28 September 2020 Camera-Ready Submission: 09 October 2020 Conference Dates: 10-14 December 2020 TOPICS : The HPBench topics of interest include, but are not limited to -Open Platforms for Parallel and Distributed Application Benchmarking and Optimization -Benchmarking on the Cloud -Benchmarking of Clusters, Supercomputers, and large-scale systems -Benchmarking the Performance of I/O -Benchmarking of Energy and Energy Efficiency -Benchmarking Web Services -Virtualization for Distributed Benchmarking -Data Distribution for Benchmarking -Performance results of benchmarks on modern platforms -Scalability Aspects of Benchmarking Parallel Applications on Parallel and Distributed Systems -Benchmarking of Parallel Scientific and Business Applications -Performance of Benchmarking Applications (Eg: NAS parallel benchmarks) -Techniques, frameworks and results concerning the benchmarking of library packages -Tools and frameworks for performance modeling systems and applications -Tools and frameworks for simulation, measurement and monitoring -Performance Measurements, Monitoring, Modeling and Simulation -Domain-specific benchmarks and applications (such as image processing, pattern recognition, cryptography, biometrics, differential equation solvers, signal processing and alike) -Mathematical Foundations of Benchmarking, Metrics and Heuristics SUBMISSION GUIDELINES: You are invited to submit original and unpublished research works on above and other topics related to benchmarking and high performance computing systems, including applications and cloud computing for benchmarking. Submitted papers must not have been published or simultaneously submitted elsewhere until it appears in HPCS proceedings, in the case of acceptance, or notified otherwise. Submission can be for - Regular papers, please submit a PDF copy of your full manuscript, not to exceed 8 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged an additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors' email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript. - Short papers (up to 4 pages), please submit a PDF copy of your full manuscript, not to exceed 4 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged an additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors' email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript. - Poster papers and Posters (please refer to http://hpcs2020.cisedu.info/1-call-for-papers-and-participation/call-for-po… for posters submission details) will also be considered. Please specify the type of submission you have. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments. Submit a PDF copy of your full manuscript to the special session paper submission site at https://easychair.org/conferences/?conf=hpbench2020. An acknowledgement will be sent within 48 hours of submission. GENERAL CHAIRS : Samar Aseeri, King Abdullah University of Science and Technology, Saudi Arabia Jordi Blasco, New Zealand eScience Infrastructure & Landcare Research, New Zealand Luigi Iapichino, Leibniz Supercomputing Centre (LRZ), Germany TECHNICAL PROGRAM COMMITTEE: Cosimo Anglano, Universitá del Piemonte Orientale, Italy Fabio Baruffa, Intel, Germany Ben Blamey, Uppsala University, Sweden Suren Byna, Lawrence Berkeley National Laboratory, California, USA Paul Carpenter, Barcelona Supercomputing Center, Spain Jesus Carretero, Universidad Carlos III de Madrid, Spain Douglas Doerfler, Lawrence Berkeley National Laboratory, USA Zhiyi Huang, University of Otago, New Zealand Clay Hughes, Sandia National Laboratories, USA Aleksandar Ilic, Universidade de Lisboa, Portugal Vasileios Karakasis, CSCS Swiss National Supercomputing Centre, Switzerland Bok Jik Lee, Seoul National University, Korea Sebastian Lührs, Jülich Supercomputing Centre, Forschungszentrum Jülich GmbH, Jülich, Germany Ravi Reddy Manumachu, University College Dublin, Ireland Dana Petcu, West University of Timisoara, Romania Ivan Rodero, Rutgers University, USA ********************************************************************* For more information see http://conf.cisedu.info/rp/hpcs20/2-conference/special-sessions/session02-h… Kind Regards -- Samar Aseeri, PhD Computational Scientist Extreme Computing Research Center (ECRC) Building 1 -Office: 0128 *King Abdullah University of Science & Technology* Thuwal, Saudi Arabia -- This message and its contents, including attachments are intended solely for the original recipient. If you are not the intended recipient or have received this message in error, please notify me immediately and delete this message from your computer system. Any unauthorized use or distribution is prohibited. Please consider the environment before printing this email.

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Maple Conference 2020 Registration
by Juergen Gerhard 25 Aug '20

25 Aug '20

[Maple Conference 2020]<http://www.maplesoft.com/?p=TC-9719> View this email as a webpage. <%25%25view_online%25%25> [Registration is now OPEN Maple Conference 2020 November 2-6, 2020 | Virtual Event Attend this year's Maple Conference virtually and for FREE! Discover all the ways that Maple has improved education and research worldwide, and see new technologies like Maple Learn and the Maple Calculator. Connect with Maple experts and users alike, without ever leaving your house! Register Now! - Description: https://www.maplesoft.com/mapleconference/images/bk4.jpg] [Facebook]<http://www.facebook.com/maplesoft> [Twitter]<http://www.twitter.com/maplesoft> [LinkedIn]<http://www.linkedin.com/groups?home=&gid=1782256> [YouTube]<http://www.youtube.com/MaplesoftVideo> [MaplePrimes]<http://www.mapleprimes.com/?p=TC-9719> [MaplePrimes]<https://www.instagram.com/maplemathmatters/?p=TC-9719> Unsubscribe <%25%25unsubscribe%25%25> | Manage Subscription <http://www.maplesoft.com/subscribers/subscription_list.aspx?p=TC-9719> | Privacy Policy<http://www.maplesoft.com/privacy/?p=TC-9719> [http://www.maplesoft.com/email/socialmedia/Maplesoft_logo_Grey-sm.png]<http://www.maplesoft.com/?p=TC-9719> © 2020 Maplesoft, a division of Waterloo Maple, Inc. 615 Kumpf Drive, Waterloo, ON, Canada, N2V1K8 customerservice(a)maplesoft.com<mailto:customerservice@maplesoft.com> | 1-800-267-6583

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CFP: HiPar20 Workshop co-located with SC20 - Submission deadline August 31st
by Rizzi, Francesco NMN 21 Aug '20

21 Aug '20

Apologies for the multiple copies of this. ******************************************************************** Call for Participation Workshop on Hierarchical Parallelism for Exascale Computing ---HiPar20--- Held in conjunction with SC20 - virtual event In cooperation with: IEEE and TCHPC. www.hipar.net ******************************************************************** ================================ Summary ================================ High Performance Computing (HPC) platforms are evolving towards having fewer but more powerful nodes, driven by the increasing number of physical cores in multiple sockets and accelerators. The boundary between nodes and networks is starting to blur, with some nodes now containing tens of compute elements and memory sub-systems connected via a memory fabric. The immediate consequence is an increase in complexity due to ever more complex architectures (e.g., memory hierarchies), novel accelerator designs, and energy constraints. Spurred largely by this trend, hierarchical parallelism is gaining momentum. This approach embraces, rather than avoiding, the intrinsic complexity of current and future HPC systems by exploiting parallelism at all levels: compute, memory and network. This workshop focuses on hierarchical parallelism. It aims to bring together application, hardware, and software practitioners proposing new strategies to fully exploit computational hierarchies, and examples to illustrate their benefits to achieve extreme scale parallelism. ================================ Scope and Aims ================================ HiPar20 is designed to showcase new studies, approaches, and cutting-edge ideas on hierarchical parallelism for extreme-scale computing. We welcome papers and talks from the HPC community addressing the use of emerging architectures — focusing particularly on those characterized by fewer but more powerful nodes as well as systems with hierarchical network with tiered communication semantics. Specifically, the emphasis is on the design, implementation, and application of programming models for multi-level parallelism, including abstractions for hierarchical memory access, heterogeneity, multi-threading, vectorization, and energy efficiency, as well as scalability and performance studies thereof. Of particular interest are models addressing these concerns portably: providing ease of programming and maintaining performance in the presence of varied accelerators, hardware configurations, and execution models. Studies that explore the merits of specific approaches to addressing these concerns, such as generic programming or domain specific languages, are also in scope. The workshop is not limited to the traditional HPC software community. As one example, another key topic is the use of hierarchical parallelism in dealing with the challenges arising in machine learning due to the growing importance of this field, the large scale of systems tackled in that area, and the increasing interest from more traditional HPC areas. A goal of HiPar20 is to highlight not just success stories but also discuss drawbacks and challenges. HiPar20 welcomes HPC practitioners from all areas, ranging from hardware and compiler experts to algorithms and software developers, to present and discuss the state of the art in emerging approaches to utilize multi-level parallelism for extreme scale computing. ================================ Topics ================================ Submissions are encouraged in, but not limited to the following areas: * Hierarchical work scheduling and execution; * Hardware, software, and algorithmic advances for efficient use of memory hierarchies, multi-threading and vectorization; * Efficient use of nested parallelism, for example CUDA dynamic parallelism, for large scale simulations; * Programming heterogeneous nodes; * Leading-edge programming models, for example fully distributed task-based models and hybrid MPI+X, with X representing shared memory parallelism via threads, vectorization, tasking or parallel loop constructs. * Implementations of algorithms that are natural fits for nested work (for example approaches that use recursion); * Challenges and successes in managing computing hierarchies; * Examples demonstrating effective use of the combination of inter-node and intra-node parallelism; * Novel approaches leveraging asynchronous execution to maximize efficiency; * Challenges and successes of porting of existing applications to many-core and heterogeneous platforms; * Recent developments in compiler optimizations for emerging architectures; * Applications of hierarchical programming models from emerging AI fields, for example deep learning and extreme-scale data analytics. ================================ Submission Guidelines ================================ We solicit submissions in the following categories: (a) Regular research papers: Intended for submissions describing original work and ideas that have not appeared in another conference or journal, and are not currently under review for any other conference or journal. Regular papers must be at least (6) and must not exceed (10) letter size pages (U.S. letter – 8.5"x11"). Accepted regular papers will be published in the workshop proceedings in cooperation with IEEE TCHPC. (b) Short papers: Intended for material that is not mature enough for a full paper, to present novel, interesting ideas or preliminary results that will be formally submitted elsewhere. Short papers must not exceed four (4) pages. Short papers will NOT be included in the proceedings. Please note that: - The page limits above only apply to the core text, content-related appendices, and figures. References and reproducibility appendix do not count against the page limit. - When deciding between submissions with comparable evaluations, priority will be given to those with higher quality of presentation and whose focus relates more directly to the workshop themes. - Papers must be submitted electronically at https://submissions.supercomputing.org/ and must follow the IEEE format: www.ieee.org/conferences/publishing/templates.html ================================ Reproducibility Initiative ================================ HiPar20 follows the SC20 reproducibility and transparency initiative. The SC20 details can be found at: https://sc20.supercomputing.org/submit/transparency-reproducibility-initiat…. HiPar20 requires all submission to include an Artifact Description (AD) Appendix. Note that the AD will be auto-generated from author responses to a form embedded in the online submission system. The Artifact Evaluation (AE) remains optional. We also encourage authors to follow the transparency initiative for two reasons: (a) it helps the authors themselves with the actual writing and structuring of the paper to express the research process; (b) it helps readers understand the thinking process used by the authors to plan, obtain and explain their results. ================================ HiPar20 will be virtual ================================ SCC20 will be fully virtual: https://sc20.supercomputing.org/2020/07/27/sc20-virtual-event-announced-by-… Please refer to our website www.hipar.net for latest updates. ================================ Important dates ================================ Submission Deadline: August 31, 2020 (AoE) Author Notification: September 14, 2020 Camera Ready: October 5, 2020 Final Program: October 9, 2020 Workshop Date: November 11-13, 2020 (details TBD) ================================ Chairs and Committees ================================ Workshop chair: - Francesco Rizzi NexGen Analytics Organizing Committee: - D.S. Hollman Sandia National Labs - Lee Howes Facebook - Xiaoye Sherry Li Lawrence Berkeley National Lab Program Committee Chairs: - Christian Trott Sandia National Labs - Filippo Spiga NVIDIA Program Committee: - Mark Bull EPCC - Carlo Cavazzoni CINECA - Benjamin Cumming CSCS - Chris Forster NVIDIA - Marta Garcia Gasulla BSC - Anja Gerbes Goethe Uni.Frankfurt - Mark Hoemmen Stellar Science - Toshiyuki Imamura RIKEN - Guido Juckeland Helmholtz Center - Hartmut Kaiser LSU - Vivek Kale Brookhaven Labs - Jonathan Lifflander Sandia National Labs - James Lin Shanghai J.Tong Univ. - Aram Markosyan Xilinx - Rui Oliveira INESC TEC - Philippe Pebay NexGen Analytics - Zhiqi Tao Intel - Flavio Vella Univ. of Bozen - Michèle Weiland EPCC - Jeremiah Wilke Sandia National Labs ================================ Contact information: ================================ For questions, please email us at: hiparws(a)gmail.com

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Using Artificial Intelligence to read the mind of pets!
by Uwe Aickelin 20 Aug '20

20 Aug '20

Have you ever wondered what your pet is thinking? Researchers at the University of Melbourne’s School of Computing and Information Systems have developed an app for that!! It is called HappyPets and uses artificial intelligence (convolutional neural networks) to analyse and interpret the facial expressions of pets. And, yes, dogs are easier to read than cats! You can read more about how it works here: https://pursuit.unimelb.edu.au/articles/ever-wondered-what-your-pet-is-thin… And download the free app here: IOS: https://apps.apple.com/au/app/happy-pets/id1515202735 Android: https://play.google.com/store/apps/details?id=au.edu.unimelb.eresearch.happ… A bit of fun, but perhaps also a good example for teaching the wide capabilities of AI?! Professor Uwe Aickelin | Head of School of Computing and Information Systems Melbourne School of Engineering Level 8, Doug McDonell Building, 168 Grattan Street The University of Melbourne, Victoria 3010 Australia T: +61 3 8344 3635 E: uwe.aickelin(a)unimelb.edu.au<mailto:uwe.aickelin@unimelb.edu.au> http://aickelin.com/ | http://linkedin.com/in/aickelin I acknowledge the Traditional Owners of the land on which I work, and pay my respects to the Elders, past and present. CRICOS: 00116K This email and any attachments may contain personal information or information that is otherwise confidential or the subject of copyright. Any use, disclosure or copying of any part of it is prohibited. The University does not warrant that this email or any attachments are free from viruses or defects. Please check any attachments for viruses and defects before opening them. If this email is received in error, please delete it and notify us by return email. [signature_1111626909]<https://eng.unimelb.edu.au/about/join-mse/current-opportunities#current-opp…>

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CfPart: European Dependable Computing Conference - EDCC 2020
by Alexander Romanovsky 17 Aug '20

17 Aug '20

The 16th European Dependable Computing Conference (EDCC 2020) September 7-10, 2020 Virtual Event - Call for Participation http://edcc.dependability.org/ A unique opportunity to learn more about the current work on dependability at no cost! The European Dependable Computing Conference (EDCC) is a leading venue for presenting and discussing the latest research, industrial practice and innovations in dependable and secure computing. The EDCC is a unique forum for researchers and practitioners to present and discuss their latest research results on theory, techniques, systems, and tools for the design, validation, operation and evaluation of dependable and secure computing systems. Intel and Fraunhofer IKS are covering the cost of the proceedings and all organisational expenses. Hence, the participation is free of charge. But you will need to register at http://edcc.dependability.org/registration.html. The EDCC technical program spans over three half days (Sept 8-10, 14h -17h45). It includes three invited talks: - Towards Universal Safety Guarantees of Decision Making in Automated Vehicles. Ignacio Alvarez. Intel Labs. - Safety of Autonomous Driving Systems. Alex Haag. AID GmbH. - Public Transport: Challenges and Opportunities for Dependability. Martin Rothfelder. Siemens AG. and twenty one technical presentations selected by the Program Committee. More information about the program could be found here: http://edcc.dependability.org/program.html Five EDCC workshops are organised on September 7: - AI4RAILS - 1st International Workshop on Artificial Intelligence for RAILwayS - DREAMS - Dynamic Risk managEment for Autonomous Systems - DSOGRI - 2nd International Workshop on Dependable SOlutions for Intelligent Electricity Distribution GRIds - SERENE - 12th International Workshop on Software Engineering for Resilient Systems - TAIWAN-DCC - 1st International Workshop on Technology of AI and Wireless Advanced Networking: Dependable Computing and Communication General chairs: Michael Paulitsch, Intel Mario Trapp, Fraunhofer Program Committee chair: Elena Troubitsyna, KTH Sweden Steering Committee chair: Karama Kanoun, LAAS Workshop chair: Simona Bernardi, University of Zaragoza Publicity chair: Alexander Romanovsky, Newcastle University Publication chair: Miguel Pardal, Universidade de Lisboa Local Organization chairs: Veronika Seifried, Fraunhofer IKS Kerstin Alexander, Intel For more information, visit: http://edcc.dependability.org/

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HPBench 2020 Online Special Session CFP
by Samar Aseeri 17 Aug '20

17 Aug '20

Dear Sir, dear Madam, We accept papers, short papers, poster papers and posters (see below submission guidelines). There will be outstanding paper and poster awards as well. Please, can you pass this announcement also to interested colleagues. Kind regards ========================================================================== CALL FOR PAPERS The 7th Special Session on High Performance Computing for Application Benchmarking and Optimization (HPBench 2020) As part of the International Conference on High Performance Computing & Simulation (HPCS 2020) http://hpcs2020.cisedu.info/ or http://conf.cisedu.info/rp/hpcs20 Barcelona, Spain (Virtual/Online event) ========================================================================== Benchmarking is an essential aspect of modern high performance computing and computational science, and as such, it provides a means for quantifying and comparing the performance of different computer systems. With a large combination of aspects to benchmark, all the way from the capability of a single core, to cluster configuration, and to various software configurations, the benchmarking process is more of an art than science. However, the results of this process drive modern science and are vital for the community to draw sensible conclusions on the performance of applications and systems. This special session focuses on research work aimed at benchmarking modern parallel and distributed systems for addressing a number of real world problems. As such, contributions concerning the definition of new open platforms, new benchmarks to match modern architectural evolutions, studies on the aspects of benchmarking different aspects of systems (from raw runtime performance to energy consumption to energy consumed per data movement) and mathematical foundations of benchmarking are sought. IMPORTANT DATES : Papers Due: 07 September 2020 - Extended Author Notification: 28 September 2020 Camera-Ready Submission: 09 October 2020 Conference Dates: 10-14 December 2020 TOPICS : The HPBench topics of interest include, but are not limited to -Open Platforms for Parallel and Distributed Application Benchmarking and Optimization -Benchmarking on the Cloud -Benchmarking of Clusters, Supercomputers, and large-scale systems -Benchmarking the Performance of I/O -Benchmarking of Energy and Energy Efficiency -Benchmarking Web Services -Virtualization for Distributed Benchmarking -Data Distribution for Benchmarking -Performance results of benchmarks on modern platforms -Scalability Aspects of Benchmarking Parallel Applications on Parallel and Distributed Systems -Benchmarking of Parallel Scientific and Business Applications -Performance of Benchmarking Applications (Eg: NAS parallel benchmarks) -Techniques, frameworks and results concerning the benchmarking of library packages -Tools and frameworks for performance modeling systems and applications -Tools and frameworks for simulation, measurement and monitoring -Performance Measurements, Monitoring, Modeling and Simulation -Domain-specific benchmarks and applications (such as image processing, pattern recognition, cryptography, biometrics, differential equation solvers, signal processing and alike) -Mathematical Foundations of Benchmarking, Metrics and Heuristics SUBMISSION GUIDELINES: You are invited to submit original and unpublished research works on above and other topics related to benchmarking and high performance computing systems, including applications and cloud computing for benchmarking. Submitted papers must not have been published or simultaneously submitted elsewhere until it appears in HPCS proceedings, in the case of acceptance, or notified otherwise. Submission can be for - Regular papers, please submit a PDF copy of your full manuscript, not to exceed 8 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged an additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors' email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript. - Short papers (up to 4 pages), please submit a PDF copy of your full manuscript, not to exceed 4 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged an additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors' email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript. - Poster papers and Posters (please refer to http://hpcs2020.cisedu.info/1-call-for-papers-and-participation/call-for-po… for posters submission details) will also be considered. Please specify the type of submission you have. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments. Submit a PDF copy of your full manuscript to the special session paper submission site at https://easychair.org/conferences/?conf=hpbench2020. An acknowledgement will be sent within 48 hours of submission. GENERAL CHAIRS : Samar Aseeri, King Abdullah University of Science and Technology, Saudi Arabia Jordi Blasco, New Zealand eScience Infrastructure & Landcare Research, New Zealand Luigi Iapichino, Leibniz Supercomputing Centre (LRZ), Germany TECHNICAL PROGRAM COMMITTEE: Cosimo Anglano, Universitá del Piemonte Orientale, Italy Fabio Baruffa, Intel, Germany Ben Blamey, Uppsala University, Sweden Suren Byna, Lawrence Berkeley National Laboratory, California, USA Paul Carpenter, Barcelona Supercomputing Center, Spain Jesus Carretero, Universidad Carlos III de Madrid, Spain Douglas Doerfler, Lawrence Berkeley National Laboratory, USA Zhiyi Huang, University of Otago, New Zealand Clay Hughes, Sandia National Laboratories, USA Aleksandar Ilic, Universidade de Lisboa, Portugal Vasileios Karakasis, CSCS Swiss National Supercomputing Centre, Switzerland Bok Jik Lee, Seoul National University, Korea Sebastian Lührs, Jülich Supercomputing Centre, Forschungszentrum Jülich GmbH, Jülich, Germany Ravi Reddy Manumachu, University College Dublin, Ireland Dana Petcu, West University of Timisoara, Romania Ivan Rodero, Rutgers University, USA ********************************************************************* For more information see http://conf.cisedu.info/rp/hpcs20/2-conference/special-sessions/session02-h… Kind Regards -- Samar Aseeri, PhD Computational Scientist Extreme Computing Research Center (ECRC) Building 1 -Office: 0128 *King Abdullah University of Science & Technology* Thuwal, Saudi Arabia -- This message and its contents, including attachments are intended solely for the original recipient. If you are not the intended recipient or have received this message in error, please notify me immediately and delete this message from your computer system. Any unauthorized use or distribution is prohibited. Please consider the environment before printing this email.

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[CFP] IA^3 2020 - 10th SC Workshop on Irregular Applications: Architectures and Algorithms - UPDATED
by Tumeo, Antonino 14 Aug '20

14 Aug '20

[Please accept our apologies if you receive multiple copies of this message.] !!!!!!!!! NEWS: WORKSHOP GOING VIRTUAL; PARCO SPECIAL ISSUE !!!!!!!! IA^3 2020 10th Workshop on Irregular Applications: Architectures and Algorithms http://hpc.pnl.gov/IA3 November 11, 2020 Virtual Workshop In conjunction with SC20 Sponsored by IEEE TCHPC -------------------- Call for Papers -------------------- Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers. Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Emerging supercomputing applications are moving towards a convergence of scientific simulation, data analytics, and learning algorithms, mixed in various ways. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years. This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to: - Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors - Network architectures and interconnect (including high-radix networks, optical interconnects) - Novel memory architectures and designs (including processors-in memory) - Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) - Modeling, simulation and evaluation of novel architectures with irregular workloads - Innovative algorithmic techniques - Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.) - Impact of irregularity on machine learning approaches - Parallelization techniques and data structures for irregular workloads - Data structures combining regular and irregular computations (e.g., attributed graphs) - Approaches for managing massive unstructured datasets (including streaming data) - Languages and programming models for irregular workloads - Library and runtime support for irregular workloads - Compiler and analysis techniques for irregular workloads - High performance data analytics applications (including graph databases and solutions that combine graph algorithms with machine learning) - Applications that integrate scientific simulation, data analytics, and learning, and require efficient execution of irregular workloads Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation. -------------------- Important Dates -------------------- Abstract Submission: August 28, 2020 (AoE) Position or Regular Paper Submission: September 4, 2020 (AoE) Notification: September 28, 2020 Artifact Evaluation: September 28, 2020 - October 10, 2020 Camera-ready: October 10, 2020 Workshop: November 11, 2020 -------------------- Submissions -------------------- Submission site: https://submissions.supercomputing.org Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers (excluding references). Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix. The templates are available at: http://www.ieee.org/conferences_events/conferences/publishing/templates.html. Accepted papers will be published in the IEEE Digital Library through IEEE TCHPC. -------------------- Artifact Description & Evaluation -------------------- This edition of the workshop invites authors of regular papers to follow a reproducibility initiative like the main SC Conference, with specific appendices for the Artifact Description (AD) and the Artifact Evaluation (AE). Please refer to the SC reproducibility page for further details on the rationale behind AD and AE: https://sc20.supercomputing.org/submit/transparency-reproducibility-initiat… Authors of regular papers will be able to use up to one (1) additional page to provide an Artifact Description (AD) Appendix, describing the details of their software environments and computational experiments to the extent that an independent person could replicate their results. Note that differently from the main conferene, this additional page is voluntary (not mandatory - i.e., if a paper has no computational results, do not attach it) for the workshop, and must focus only on details on software environments and methods to execute the experiments. It should not add details on the proposed technical approaches. Additionally, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation (AE) process. The process is voluntary, but authors that will participate in the AE will be eligible for the Best Paper Award of the workshop. Supporting materials for the AE include access to the actual software artifact, shared publicly (for example, through the CK - Collective Knowledge - https://github.com/ctuning/ck format), and two (2) further additional pages of the paper that details how to reproduce the results of the paper. For details on how to submit supporting materials to the AE process, please refer to: http://ctuning.org/ae/submission.html. Authors participating in the AE will receive an assessment of the artifact, and the related badge on their paper. For any additional question on the AD and the AE please contact the Artifact Evaluation Chair, Biagio Cosenza, at bcosenza(a)unisa.it. -------------------- Special Issue -------------------- Authors of papers accepted to the workshop will also be invited to submit extended version of their papers to a Special Issue of the journal of Parallel Computing (ParCO) on Hardware/Software Co-design for Sparse and Irregular Applications. Submissions for the special issue with open December 1, 2020 and will close on March 1, 2021. For more information on this special issue, please visit the special issue page and/or contact the guest co-editors, Flavio Vella (flavio.vella(a)unibz.it) and Antonino Tumeo (antonino.tumeo(a)pnnl.gov). https://www.journals.elsevier.com/parallel-computing/call-for-papers/hardwa… -------------------- Organizers -------------------- Antonino Tumeo (PNNL), antonino.tumeo(a)pnnl.gov John Feo (PNNL), john.feo(a)pnnl.gov Vito Giovanni Castellana (PNNL), vitoGiovanni.castellana(a)pnnl.gov -------------------- Proceedings Chair -------------------- Marco Minutoli (PNNL and WSU), marco.minutoli(a)pnnl.gov -------------------- Artifact Evaluation Chair -------------------- Biagio Cosenza (University of Salerno), bcosenza(a)unisa.it -------------------- Technical Program Committee -------------------- Nesreen Ahmed, Intel, US Johnathan Alsop, AMD, US Eishi Arima, University of Tokyo, JP Scott Beamer, University of California, Santa Cruz, US Jonathan Beard, ARM, US Michela Becchi, North Carolina State University, US Sanjukta Bhowmick, University of North Texas, US Erik Boman, SNL, US David Brooks, Harvard University, US Prerna Budhkar, Intel, US Aydin Buluc, LBNL, US Anastasiia Butko, LBNL, US Assefaw Gebremedhin, Washington State University, US Cat Graves, HPE, US Rajiv Gupta, University of California, Riverside, US Peter M. Kogge, Notre Dame University, US John Leidel, Tactical Computing Lab, US Kamesh Madduri, Pennsylvania State University José Moreira, IBM Research, US Miquel Moretó, Barçelona Supercomputing Center, ES Maxim Naumov, Facebook, US Fanny Nina-Paravecino, Microsoft, US Roger Pearce, LLNL, US Keshav Pingali, University of Texas, Austin, US Alejandro Rico, ARM, US Jason Riedy, Georgia Tech, US Thomas B. Rolinger, University of Maryland, US Kentaro Sano, RIKEN, JP John Shalf, LBNL, US Shaden Smith, Microsoft, US Tyler Sorensen, University of California, Santa Cruz, US Ruud van der Pas, Oracle, NL Ana Lucia Varbanescu, University of Amsterdam, NL Flavio Vella, Free University of Bozen, IT Other members TBD

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REMINDER - Call for Nominations: 2020 IEEE CS TCHPC ECR Award for Excellence in HPC
by Vladimir Getov 12 Aug '20

12 Aug '20

Call for Nominations: 2020 IEEE CS TCHPC Early Career Researchers Award for Excellence in High Performance Computing The IEEE Computer Society TCHPC Early Career Researchers Award for Excellence in High Performance Computing recognizes up to 3 individuals who have made outstanding, influential, and potentially long-lasting contributions in the field of high-performance computing within 5 years of receiving their PhD degree as of January 01 of the year of the award. It is sponsored by the IEEE Computer Society Technical Consortium on High Performance Computing (TCHPC) and its member Technical Committees: •Technical Committee on Parallel Processing (TCPP) •Technical Committee on Computer Communications (TCCC) •Technical Committee on Distributed Processing (TCDP) •Technical Committee on Cloud Computing (TCCLD) •Task Force on Rebooting Computing (TFRC) •Technical Committee on Computational Life Sciences (TCCLS) Nominations: A candidate must be nominated by member(s) of the community. An individual may nominate at most one candidate for this award. The nomination application must be submitted via email to tchpc-awards(a)computer.org as a single PDF file and should contain the following details: 1.Name/email of person making the nomination (self-nominations are not eligible). 2.Name/email of candidate for whom the award is recommended. 3.A statement by the nominator (maximum of 500 words) as to why the nominee is highly deserving of the award. Note that since the award is for outstanding contributions, the statement and supporting letters should address what the contributions are and why they are both outstanding and significant. The nomination should also list the names and email of up to 3 persons who have provided letters supporting the nomination. 4.CV of the nominee. 5.Up to three letters of support from persons other than the nominator – these should be collected by the nominator and included in the nomination. Important Dates: •Nomination Deadline: August 15, 2020 •Results Notification: September 15, 2020 Award Selection Committee: The award selection committee consists of: •Rosa M. Badia, Barcelona Supercomputing Center, Spain •Tom Conte, Georgia Institute of Technology, USA •Yufei Ding, University of California Santa Barbara, USA •Vladimir Getov, University of Westminster, UK (Chair) •Xu Liu, College of William & Mary, USA •Guillaume Pallez, Inria, France •Happy Sithole, National Integrated Cyber-Infrastructure (NICIS), South Africa Note that members of the selection committee cannot be nominators or provide support letters. Award & Presentation Note: Awardees will be presented a plaque and will be recognized by IEEE Computer Society and TCHPC websites, newsletters and archives. The awards will be presented at the SC20 conference that will be held virtually during November 9 – 19, 2020. Details of the conference can be found at http://sc20.supercomputing.org/. For more information, please send email to tchpc-awards(a)computer.org. The University of Westminster is a charity and a company limited by guarantee. Registration number: 977818 England. Registered Office: 309 Regent Street, London W1B 2HW. This message and its attachments are private and confidential. If you have received this message in error, please notify the sender and remove it and its attachments from your system.

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