- computational.science - lists.iccsa.org

[CFP] IA^3 2018 - Deadline extended to September 5
by Tumeo, Antonino 22 Aug '18

22 Aug '18

[Apologies if you receive multiple copies of this CFP] — NEWS: DUE TO NUMEROUS REQUESTS, WE HAVE EXTENDED THE DEADLINE FOR ABSTRACTS AND PAPERS TO SEPTEMBER 5! — IA^3 2018 8th Workshop on Irregular Applications: Architectures and Algorithms http://hpc.pnl.gov/IA3 In Conjuction with SC18 Sponsored by IEEE TCHPC -------------------- Call for Papers -------------------- Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers. Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years. This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to: - Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors - Network architectures and interconnect (including high-radix networks, optical interconnects) - Novel memory architectures and designs (including processors-in memory) - Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) - Modeling, simulation and evaluation of novel architectures with irregular workloads - Innovative algorithmic techniques - Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.) - Impact of irregularity on machine learning approaches - Parallelization techniques and data structures for irregular workloads - Data structures combining regular and irregular computations (e.g., attributed graphs) - Approaches for managing massive unstructured datasets (including streaming data) - Languages and programming models for irregular workloads - Library and runtime support for irregular workloads - Compiler and analysis techniques for irregular workloads - High performance data analytics applications, including graph databases Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation. -------------------- Important Dates -------------------- Abstract Submission: September 5, 2018 (EXTENDED) Position or Regular Paper Submission: September 5, 2018 (EXTENDED) Notification: September 28, 2018 Camera-ready: October 10, 2018 Workshop: November 12, 2018 Submissions Submission site: https://submissions.supercomputing.org<https://submissions.supercomputing.org/> Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers including figures, tables and references. Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix. The workshop proceedings will be published through IEEE TCHPC and will be included in the IEEE Xplore digital library. The templates are available at: http://www.ieee.org/conferences_events/conferences/publishing/templates.html. -------------------- Artifact Description & Evaluation -------------------- This edition of the workshop invites authors of regular papers to follow a reproducibility initiative like the main SC Conference, with specific appendices for the Artifact Description (AD) and the Artifact Evaluation (AE). Please refer to the SC reproducibility page for further details on the rationale behind AD and AE: https://sc18.supercomputing.org/submit/sc-reproducibility-initiative/. Authors of regular papers will be able to use up to one (1) additional page to provide an Artifact Description (AD) Appendix, describing the details of their software environments and computational experiments to the extent that an independent person could replicate their results. This additional page is voluntary, and must focus only on details on software environments and methods to execute the experiments. It should not add details on the proposed technical approaches. If a paper has no computational results, the appendix only needs to mention that computational results are not part of the paper. Additionally, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation (AE) process. The process is voluntary, but authors that will participate in the AE will be eligible for the Best Paper Award of the workshop. Supporting materials for the AE include access to the actual software artifact, shared pubblicly (for example, through the CK - Collective Knowledge - https://github.com/ctuning/ck format), and two (2) further additional pages of the paper that details how to reproduce the results of the paper. For details on how to submit supporting materials to the AE process, please refer to: http://ctuning.org/ae/submission.html. Authors participating in the AE will receive an assessment of the artifact, and the related badge on their paper. For any additional question on the AD and the AE please contact the Artifact Evaluation Chair Flavio Vella at flavio(a)dividiti.com<mailto:flavio@dividiti.com>. -------------------- ACM TOPC Special Issue -------------------- Authors interested in the topics of the workshop are also invited to submit papers to the thematic Special Issue on Innovations in Systems for Irregular Applications of ACM Transactions on Parallel Computing (TOPC). We invite, in particular, authors of papers accepted to previous editions of the workshop, as well as authors of accepted papers to the upcoming edition, to submit exteded versions of their paper. Deadline for the submission to the special issue is October 31, 2018, i.e., after the notification for this year edition of the workshop, but slightly before the workshop itself. For more information on the TOPC Special Issue on Innovations in Systems for Irregular Applications, including details on submissions and important dates, please consult the following link: http://hpc.pnl.gov/TOPCSI/. -------------------- Organizers -------------------- Antonino Tumeo (PNNL), antonino.tumeo(a)pnnl.gov<mailto:antonino.tumeo@pnnl.gov> John Feo (PNNL/NIAC), john.feo(a)pnnl.gov<mailto:john.feo@pnnl.gov> Vito Giovanni Castellana (PNNL), vitoGiovanni.castellana(a)pnnl.gov<mailto:vitoGiovanni.castellana@pnnl.gov> -------------------- Proceedings Chair -------------------- Marco Minutoli (PNNL and WSU), marco.minutoli(a)pnnl.gov<mailto:marco.minutoli@pnnl.gov> -------------------- Artifact Evaluation Chair -------------------- Favio Vella (DIVIDITI), flavio(a)dividiti.com<mailto:flavio@dividiti.com> -------------------- Technical Program Committee -------------------- Nesreen Ahmed, Intel, US Kubilay Atasu, IBM Zurich, CH Scott Beamer, University of California, Santa Cruz, and LBNL, US Michela Becchi, North Carolina State University, US Sanjukta Bhowmick, University of Nebraska Omaha, US Erik Boman, SNL, US David Brooks, Harvard University, US Aydin Buluc, LBNL, US Joe Eaton, NVIDIA, US Rajiv Gupta, UC Riverside, US Arif Khan, PNNL, US Farzad Khorasani, Georgia Tech, US Peter M. Kogge, University of Notre Dame, US Manoj Kumar, IBM TJ Watson, US John Leidel, Tactical Computing Labs, US Kamesh Madduri, Pennsylvania State University, US Naoya Maruyama, LLNL, US Miquel Moretó, Barçelona Supercomputing Center, ES Maxim Naumov, Facebook, US Fanny Nina-Paravecino, Northeastern University, US Sreepathi Pai, Rochester University, US Roger Pearce, LLNL, US Miquel Pericas, Chalmers University of Technology, SE Keshav Pingali, University of Texas at Austin, US Viktor K. Prasanna, University of Southern California, US Jason Riedy, Georgia Tech, US John Shalf, LBNL, US Shaden Smith, Intel, US Edgar Solomonik, University of Illinois at Urbana-Champaign, US Bora Uçar, French National Center for Scientific Research, FR Ruud van der Pas, Oracle, NL Ana Lucia Varbanescu, University of Amsterdam, NL Cheng Wang, Microsoft, US Jishen Zhao, University of California, San Diego, US

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Final CFP: IEEE ISPA2018 (Parallel and Distributed Processing with Applications), Dec. 2018, Melbourne, Australia
by Jesson Butt 22 Aug '18

22 Aug '18

Final Call for papers: The 16th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2018), 11-13 Dec. 2018, Melbourne, Australia. Website: http://www.swinflow.org/confs/2018/ispa/ Key dates: Submission Deadline: August 31, 2018 (11:59pm UTC/GMT, firm) Notification: September 30, 2018 Final Manuscript Due: October 15, 2018 Submission site: http://www.swinflow.org/confs/2018/ispa/submission.htm Publication: Proceedings will be published by IEEE CS Press. Special issues: Distinguished papers will be selected for special issues in Information Sciences, Future Generation Computer Systems, Journal of Parallel and Distributed Computing, Concurrency and Computation: Practice and Experience =========== Introduction The IEEE ISPA 2018 (16th IEEE International Symposium on Parallel and Distributed Processing with Applications) is a forum for presenting leading work on parallel and distributed computing and networking, including architecture, compilers, runtime systems, applications, reliability, security, parallel programming models and much more. During the symposium, scientists and engineers in both academia and industry are invited to present their work on concurrent and parallel systems (multicore, multithreaded, heterogeneous, clustered systems, distributed systems, grids, clouds, and large scale machines). The 16th IEEE ISPA follows the tradition of previous successful IEEE ISPA conferences in the years from 2003 to 2017 in Asia, Europe, Australia and North America. It will feature sessions of regular presentations, workshops, tutorials and keynote speeches. IEEE ISPA 2018 is sponsored by the IEEE Technical Committee on Scalable Computing (TCSC) and the IEEE Computer Society. IEEE ISPA is particularly interested in research addressing heterogeneous computing with the use of accelerators, mobile computing, approximate computing, tools and methodologies to improve the quality of parallel programming and applying generic computing approaches to networks, in particular Software Defined networking and its applications. Scope and Topics *(1) Systems and Architectures Track* - Cloud computing and data center technology - Migration of computations - Multi-clouds environments, cloud federation, interoperability - Energy management and Green Computing - Wireless and mobile networks - Internet-Of-Things (IoT) - Social Networks, crowdsourcing, and P2P systems *(2) Technologies and Tools Track* - Building block processors: FPGA, multicore, GPU, NoC, SoC - Parallel and distributed algorithms - Tools/environments for parallel/distributed software development - Novel parallel programming paradigms - Programming models for cloud services and applications - Code generation and optimization - Compilers for parallel computers - Middleware and tools - Scheduling and resource management - Performance simulations, measurement, and evaluations - Reliability, fault tolerance, dependability, and security *(3) Applications Track* - High-performance scientific and engineering computing - Grid and cluster computing - Pervasive and ubiquitous computing - Databases, data mining, and data management - Big data and business analytics - Scientific cloud systems and services - Internet computing and web services - Application scenarios of IoT and ubiquitous computing - Experience with computational, workflow and data-intensive applications - Software Defined Networks and its applications Submission Guidelines Submissions must include an abstract, keywords, the e-mail address of the corresponding author and should not exceed 8 pages for main conference, including tables and figures in IEEE CS format. The template files for LATEX or WORD can be downloaded here. All paper submissions must represent original and unpublished work. Each submission will be peer reviewed by at least three program committee members. Submission of a paper should be regarded as an undertaking that, should the paper be accepted, at least one of the authors will register for the conference and present the work. Submit your paper(s) in PDF file at the submission site: http://www.swinflow.org/confs/2018/ispa/submission.htm. Publications Accepted and presented papers will be included into the IEEE Conference Proceedings published by IEEE CS Press. Authors of accepted papers, or at least one of them, are requested to register and present their work at the conference, otherwise their papers may be removed from the digital libraries of IEEE CS and EI after the conference. Distinguished papers will be selected for special issues in Information Sciences, Future Generation Computer Systems, Journal of Parallel and Distributed Computing, Concurrency and Computation: Practice and Experience. Honorary Chairs Wanlei Zhou, Deakin University, Australia Albert Zomaya, The University of Sydney, Australia General Chairs Geoffrey Fox, Indiana University, USA Beniamino Di Martino, Universita' della Campania "Luigi Vanvitelli", Italy Laurence Yang, St. Francis Xavier University, Canada Program Chairs Mianxiong Dong, Muroran Institute of Technology, Japan Rajiv Ranjan, Newcastle University, UK Massimo Cafaro, University of Salento, Lecce, Italy Workshop Chairs Young Choon Lee, Macquarie University, Australia Wei Zheng, Xiamen University, China

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A Practical Introduction to Debugging Webinar
by Mary Ann Leung, Ph.D. 17 Aug '18

17 Aug '18

The Sustainable Horizons Institute Webinar Series Proudly Presents: "A Practical Introduction to Debugging!" Join us on Friday, August 24th, 2018 from 2:00 pm -3:00 pm CST. We are privileged to have Dr. Jeremy Melvin host a webinar on debugging. During this webinar, you will learn about strategies for handling bugs in your software, tools to aid in debugging, such as GDB (GNU Debugger) and other resources, and the opportunity to take part in an interactive debugging session using GDB. Dr. Jeremy Melvin is an ICES postdoctoral fellow at the University of Texas at Austin. He received his Ph.D in Computational Applied Mathematics from Stony Brook University. His research interests are focused on developing tools and models to improve the predictive capabilities of numerical simulations for turbulent flows in complex engineering problems. Register using the link below! https://goo.gl/forms/3P2sumYWEPwqw0Bz1 This webinar is part of a quarterly webinar series aimed toward students and early career professionals in STEM, and is organized through the Sustainable Horizons Institute. To contact the SHI Webinar Committee, please email shi.webinar(a)gmail.com

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2018 Sustainable Research Pathways (SRP) Matching and Exploratory Research Collaboration Workshop
by Mary Ann Leung, Ph.D. 14 Aug '18

14 Aug '18

We are pleased to announce 2018 Sustainable Research Pathways (SRP) program is now accepting applications from faculty at US degree granting academic institutions. Come to Berkeley Lab to learn about summer research opportunities for you and/or your students at a Department of Energy National Laboratory SRP Matching and Exploratory Workshop To facilitate the possible matching of faculty and/or their students with lab research opportunities, selected faculty will be invited to a workshop on December 3-4, 2018, at Berkeley Lab. Computing Sciences staff and selected faculty applicants will discuss their research projects and interests in order to determine possible matches and the potential for research collaborations. This workshop, developed under a partnership between Sustainable Horizons Institute and Berkeley Lab, is designed for faculty from any US degree granting institution, including Minority Serving Institutions (MSI) and women’s, liberal arts, and community colleges, which support students such as: women, minorities, first generation scholars, and people with disabilities as well as those from under-privileged backgrounds. Faculty learn about opportunities to engage in collaborative, cutting-edge research with Berkeley Lab computing scientists. Matched faculty will be invited to apply for summer research opportunities at Berkeley lab. Faculty Benefits * Pre-workshop webinar * Travel funding for Matching and Exploratory Workshop * Meetings with Lawrence Berkeley National Laboratory staff to discuss possible research collaborations * Potential to participate in summer research as: o Faculty/student teams o Students on their own Preference is given to faculty/student teams Application requirements and other details can be found at http://shinstitute.org/srp-application/ http://cs.lbl.gov/careers/summer-student-program/ Application deadline: Friday, September 14, 2018 A brighter scientific future is on the horizon... ~.~.~.~.~.~.~.~.~.~.~.~.~.~.~.~.~.~ Mary Ann Leung, Ph.D. President Sustainable Horizons Institute 36101 Bob Hope Drive, Suite E-5170 Rancho Mirage, CA 92270 515-450-8190 office 515-203-1298 cell mleung(a)shinstitute.org http://www.shinstitute.org ~.~.~.~.~.~.~.~.~.~.~.~.~.~.~.~.~.~

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[IEEE LPWANSys] Call for Papers
by Tan Rui (Asst Prof) 09 Aug '18

09 Aug '18

================================================================================ Call for Papers IEEE LPWANSys 2018 in Conjunction with IEEE ICPADS 2018 https://ntusg-iot.github.io/lpwansys/ Sentosa, Singapore ================================================================================ The 1st Workshop on LPWAN Systems and Applications (LPWANSys 2018) will be held in conjunction with The 24th International Conference on Parallel and Distributed Systems (IEEE ICPADS 2018) during December 11-13, 2018, in Singapore. * IMPORTANT DATES Paper submission deadline: September 15, 2018 Paper notification: September 26, 2018 Camera ready: October 1, 2018 * SCOPE The emerging low-power wide-area network (LPWAN) technologies will largely increase the degree of connectivity of Internet of Things (IoT) and enable the deep penetration of smart objects into the territories that challenged the existing short-range wireless technologies, such as urban areas with dense buildings, underground structures, uninstrumented rural and wild areas, etc. With the increasingly available LPWAN platforms (e.g., LoRaWAN and NBIoT) and the relevant development tools, research shall explore the challenges, issues, and opportunities in the improvement and deployment of LPWANs. LPWANSys aims to be the premier workshop for the research on LPWAN systems and applications. It invites researchers to submit and present their original studies in various aspects of LPWAN as well as stories and learned lessons in deploying real-world LPWAN systems and applications. Topics of interest include, but are not limited to: - Narrowband channel profiling - Physical layer of LPWAN - Data link layer of LPWAN - Multi-gateway design - LPWAN performance profiling and analysis - LPWAN real-world applications - LPWAN deployment experiences - LPWAN with mobility - Security issues of LPWAN - Regulatory issues of LPWAN * SUBMISSION GUIDELINE Each submission must not exceed 6 pages in the IEEE 8.5“x11” two-column format with 10-point font, including tables, figures, and references. Submissions should be formatted using the template provided below and in PDF format. The review process is single-blind so the submissions should include author information. All submissions will be reviewed by the Program Committee members. At least one author of the accepted paper should register the workshop and present the paper in the workshop in order for the accepted paper to be included into the IEEE digital library. All accepted papers will be included in IEEEXplore and indexed by EI. Submission site: https://easychair.org/conferences/?conf=icpads2018 LaTeX template: http://icpads.sg/file/latex.zip MS Word template: http://icpads.sg/file/word.doc * ORGANIZERS - Program Co-Chairs Rui Tan (Nanyang Technological University) Jiliang Wang (Tsinghua University) Jun Huang (Peking University) - Program Committee Abusayeed Saifullah (Wayne State University) Ambuj Varshney (Uppsala University) Chenren Xu (Peking University) Gowri Sankar Ramachandran (University of Southern California) Linghe Kong (Shanghai Jiao Tong University) Mo Sha (Binghamton University) RangaRao Venkatesha Prasad (Delft University of Technology) Shibo He (Zhejiang University) Wan Du (University of California, Merced) (More PC members to be added) - Web Chair Chaojie Gu (Nanyang Technological University) -- Our sincere apologies if you receive multiple copies of the call -- ________________________________ CONFIDENTIALITY: This email is intended solely for the person(s) named and may be confidential and/or privileged. If you are not the intended recipient, please delete it, notify us and do not copy, use, or disclose its contents. Towards a sustainable earth: Print only when necessary. Thank you.

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Call for Workshop Papers and Student Research Symposium: 25th IEEE Intl Conf on High Performance Computing, Data, and Analytics (HiPC)
by Anand Panangadan 08 Aug '18

08 Aug '18

25th IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC 2018) December 17-20, 2018 Bengaluru, India www.hipc.org 2018 marks the Silver Anniversary of IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC). The conference has a history of attracting participation from reputed researchers from all over the world and receives strong industry support from companies operating globally and also established in India. In addition to the two days of industry exhibits, the sponsoring partners to the conference hold industry symposiums to bring together providers and users of HPC in a forum for presenting state-of-the-art in HPC platforms and technologies, for discussing best practices, and for exchanging experiences. CALL FOR WORKSHOP PAPERS Complementing the main technical program, HiPC workshops serve to broaden the technical scope of the conference in emerging areas of high performance computing, communication, data and analytics and their applications. Below is the listing of the workshops to be held on the first day of the conference, December 17. • Fourth Workshop on Computational Fluid Dynamics (CFD) • Workshop on Artificial Intelligence Meets Blockchain (AIMB) • First Workshop on the Convergence of High Performance Computing and Artificial Intelligence • Women in Data Science and High Performance Computing • Parallel Fast Fourier Transforms See details at http://hipc.org/workshops for workshop paper submission deadlines and formatting requirements. STUDENT RESEARCH SYMPOSIUM (SRS) SRS is aimed at stimulating and fostering student research, and providing an international forum to highlight student research accomplishments. The symposium will also provide exposure to students in the best practices in HPC in academia and industry. The symposium will feature student posters and provide students with other enriching experiences, such as workshops, industry exhibits, and demos. http://hipc.org/student-research-symposium/ ------------------------------------------------------------------------------------------------ Follow us on Twitter https://twitter.com/hipcconf Google+ https://plus.google.com/+HipcOrg Facebook https://www.facebook.com/hipc.conference/ LinkedIn https://www.linkedin.com/groups/53197/profile SPONSORSHIP: •IEEE Computer Society Technical Committee on Parallel Processing (TCPP) •HiPC Education Trust, India In cooperation with •ACM Special Interest Group on Algorithms and Computation Theory (SIGACT) •ACM Special Interest Group on Computer Architecture (SIGARCH) •FIP Working Group on Concurrent Systems •Manufacturers' Association for Information Technology (MAIT) •National Association of Software and Service Companies (NASSCOM)

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[CFP] IA^3 2018 - Deadline approaching & ACM TOPC special Issue
by Tumeo, Antonino 08 Aug '18

08 Aug '18

[Apologies if you receive multiple copies of this CFP] IA^3 2018 8th Workshop on Irregular Applications: Architectures and Algorithms http://hpc.pnl.gov/IA3 In Conjuction with SC18 Sponsored by IEEE TCHPC -------------------- Call for Papers -------------------- Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers. Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years. This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to: - Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors - Network architectures and interconnect (including high-radix networks, optical interconnects) - Novel memory architectures and designs (including processors-in memory) - Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) - Modeling, simulation and evaluation of novel architectures with irregular workloads - Innovative algorithmic techniques - Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.) - Impact of irregularity on machine learning approaches - Parallelization techniques and data structures for irregular workloads - Data structures combining regular and irregular computations (e.g., attributed graphs) - Approaches for managing massive unstructured datasets (including streaming data) - Languages and programming models for irregular workloads - Library and runtime support for irregular workloads - Compiler and analysis techniques for irregular workloads - High performance data analytics applications, including graph databases Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation. -------------------- Important Dates -------------------- Abstract Submission: August 22, 2018 Position or Regular Paper Submission: August 29, 2018 Notification: September 28, 2018 Camera-ready: October 10, 2018 Workshop: November 12, 2018 Submissions Submission site: https://submissions.supercomputing.org<https://submissions.supercomputing.org/> Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers including figures, tables and references. Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix. The workshop proceedings will be published through IEEE TCHPC and will be included in the IEEE Xplore digital library. The templates are available at: http://www.ieee.org/conferences_events/conferences/publishing/templates.html. -------------------- Artifact Description & Evaluation -------------------- This edition of the workshop invites authors of regular papers to follow a reproducibility initiative like the main SC Conference, with specific appendices for the Artifact Description (AD) and the Artifact Evaluation (AE). Please refer to the SC reproducibility page for further details on the rationale behind AD and AE: https://sc18.supercomputing.org/submit/sc-reproducibility-initiative/. Authors of regular papers will be able to use up to one (1) additional page to provide an Artifact Description (AD) Appendix, describing the details of their software environments and computational experiments to the extent that an independent person could replicate their results. This additional page is voluntary, and must focus only on details on software environments and methods to execute the experiments. It should not add details on the proposed technical approaches. If a paper has no computational results, the appendix only needs to mention that computational results are not part of the paper. Additionally, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation (AE) process. The process is voluntary, but authors that will participate in the AE will be eligible for the Best Paper Award of the workshop. Supporting materials for the AE include access to the actual software artifact, shared pubblicly (for example, through the CK - Collective Knowledge - https://github.com/ctuning/ck format), and two (2) further additional pages of the paper that details how to reproduce the results of the paper. For details on how to submit supporting materials to the AE process, please refer to: http://ctuning.org/ae/submission.html. Authors participating in the AE will receive an assessment of the artifact, and the related badge on their paper. For any additional question on the AD and the AE please contact the Artifact Evaluation Chair Flavio Vella at flavio(a)dividiti.com<mailto:flavio@dividiti.com>. -------------------- ACM TOPC Special Issue -------------------- Authors interested in the topics of the workshop are also invited to submit papers to the thematic Special Issue on Innovations in Systems for Irregular Applications of ACM Transactions on Parallel Computing (TOPC). We invite, in particular, authors of papers accepted to previous editions of the workshop, as well as authors of accepted papers to the upcoming edition, to submit exteded versions of their paper. Deadline for the submission to the special issue is October 31, 2018, i.e., after the notification for this year edition of the workshop, but slightly before the workshop itself. For more information on the TOPC Special Issue on Innovations in Systems for Irregular Applications, including details on submissions and important dates, please consult the following link: http://hpc.pnl.gov/TOPCSI/. -------------------- Organizers -------------------- Antonino Tumeo (PNNL), antonino.tumeo(a)pnnl.gov<mailto:antonino.tumeo@pnnl.gov> John Feo (PNNL/NIAC), john.feo(a)pnnl.gov<mailto:john.feo@pnnl.gov> Vito Giovanni Castellana (PNNL), vitoGiovanni.castellana(a)pnnl.gov<mailto:vitoGiovanni.castellana@pnnl.gov> -------------------- Proceedings Chair -------------------- Marco Minutoli (PNNL and WSU), marco.minutoli(a)pnnl.gov<mailto:marco.minutoli@pnnl.gov> -------------------- Artifact Evaluation Chair -------------------- Favio Vella (DIVIDITI), flavio(a)dividiti.com<mailto:flavio@dividiti.com> -------------------- Technical Program Committee -------------------- Nesreen Ahmed, Intel, US Kubilay Atasu, IBM Zurich, CH Scott Beamer, LBNL, US Michela Becchi, North Carolina State University, US Sanjukta Bhowmick, University of Nebraska Omaha, US Erik Boman, SNL, US David Brooks, Harvard University, US Aydin Buluc, LBNL, US Joe Eaton, NVIDIA, US Rajiv Gupta, UC Riverside, US Arif Khan, PNNL, US Farzad Khorasani, Georgia Tech, US Peter M. Kogge, University of Notre Dame, US Manoj Kumar, IBM TJ Watson, US John Leidel, Tactical Computing Labs, US Kamesh Madduri, Pennsylvania State University, US Naoya Maruyama, LLNL, US Miquel Moretó, Barçelona Supercomputing Center, ES Maxim Naumov, Facebook, US Fanny Nina-Paravecino, Northeastern University, US Sreepathi Pai, Rochester University, US Roger Pearce, LLNL, US Miquel Pericas, Chalmers University of Technology, SE Keshav Pingali, University of Texas at Austin, US Viktor K. Prasanna, University of Southern California, US Jason Riedy, Georgia Tech, US John Shalf, LBNL, US Shaden Smith, Intel, US Edgar Solomonik, University of Illinois at Urbana-Champaign, US Bora Uçar, French National Center for Scientific Research, FR Ruud van der Pas, Oracle, NL Ana Lucia Varbanescu, University of Amsterdam, NL Cheng Wang, Microsoft, US

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CFP: IEEE BDCloud2018 (Big Data and Cloud Computing), Dec. 2018, Melbourne, Australia
by Arne Wilston 08 Aug '18

08 Aug '18

Call for papers: The 8th IEEE International Conference on Big Data and Cloud Computing ( BDCloud2018), 11-13 Dec. 2018, Melbourne, Australia. Website: http://www.swinflow.org/confs/2018/bdcloud/ Key dates: Submission Deadline: August 31, 2018 (11:59pm UTC/GMT, firm) Notification: September 30, 2018 Final Manuscript Due: October 15, 2018 Submission site: http://www.swinflow.org/confs/2018/bdcloud/submission.htm Publication: Proceedings will be published by IEEE CS Press. Special issues: Distinguished papers will be selected for special issues in Information Sciences, Future Generation Computer Systems, Journal of Parallel and Distributed Computing, Concurrency and Computation: Practice and Experience =========== Introduction Big data is an emerging paradigm applied to datasets whose size is beyond the ability of commonly used software tools to capture, manage, and process the data within a tolerable elapsed time. Such datasets are often from various sources (Variety) yet unstructured such as social media, sensors, scientific applications, surveillance, video and image archives, Internet texts and documents, Internet search indexing, medical records, business transactions and web logs; and are of large size (Volume) with fast data in/out (Velocity). More importantly, big data has to be of high value (Value) and establish trust in it for business decision making (Veracity). Cloud computing is positioning itself as an emerging platform for delivering information infrastructures and resources as IT services. Customers (enterprises or individuals) can provision and deploy Cloud services via pay-as-you-go pricing models saving huge capital investments in their own IT infrastructures. As estimated by IDC, by 2020, about 40% data globally would be touched with Cloud Computing. Cloud Computing provides strong storage, computation and distributed capability in support of Big Data processing. BDCloud (Big Data and Cloud Computing) was created to provide a prime international forum for researchers, industry practitioners and domain experts to exchange the latest advances in Big Data and Cloud Computing as well as their synergy. Scope and Topics Topics of particular interest include, but are not limited to: · Fundamentals of cloud computing · Architectural cloud models · Programming cloud models · Provisioning/pricing cloud models · Data storage and computation in cloud computing · Resource and large-scale job scheduling in cloud computing · Security, privacy, trust, risk in cloud and big data · Fault tolerance and reliability in cloud computing · Access control to cloud computing · Resource virtualisation · Monitoring and auditing in cloud · Scalable and elastic cloud services · Social computing and impacts on the cloud · Innovative HCI and touch-screen models and technologies to cloud · Mobile commerce, handheld commerce and e-markets on cloud · Intelligent/agent-based cloud computing · Migration of business applications to cloud · Energy efficient cloud architecture · Energy aware data storage and computation in cloud computing · Energy aware scheduling, monitoring, auditing in cloud · Green Cloud · Cloud use case studies · Big Data theory, applications and challenges · Big Data mining and analytics on Cloud · Big Data Infrastructure, MapReduce and Cloud Computing · Big Data visualization · Large data stream, incremental datasets on cloud · Distributed and federated datasets · NoSQL data stores and DB scalability · Big Data sharing, security, privacy and trust · Big Data placement, scheduling, and optimization · Distributed file systems for Big Data · Big Data processing, resource scheduling and SLA on Cloud · Performance characterization, evaluation and optimization · Simulation and debugging of Big Data systems · Volume, Velocity, Variety, Value and Veracity of Big Data · Storage and computation management of Big Data · Large-scale workflow management in Big Data · Data management and distributed data systems · Big data applications Submission Guidelines Submissions must include an abstract, keywords, the e-mail address of the corresponding author and should not exceed 8 pages for main conference, including tables and figures in IEEE CS format. The template files for LATEX or WORD can be downloaded here. All paper submissions must represent original and unpublished work. Each submission will be peer reviewed by at least three program committee members. Submission of a paper should be regarded as an undertaking that, should the paper be accepted, at least one of the authors will register for the conference and present the work. Submit your paper(s) in PDF file at the submission site: http://www.swinflow.org/confs/2018/bdcloud/submission.htm. Publications Accepted and presented papers will be included into the IEEE Conference Proceedings published by IEEE CS Press. Authors of accepted papers, or at least one of them, are requested to register and present their work at the conference, otherwise their papers may be removed from the digital libraries of IEEE CS and EI after the conference. Distinguished papers will be selected for special issues in Information Sciences, Future Generation Computer Systems, Journal of Parallel and Distributed Computing, Concurrency and Computation: Practice and Experience. General Chairs Xuemin Lin, The University of New South Wales, Australia Rajkumar Buyya, The University of Melbourne, Australia Laurence Yang, St. Francis Xavier University, Canada Program Chairs Zahir Tari, RMIT University, Australia Kim-Kwang Raymond Choo, The University of Texas at San Antonio, USA Vladimir Vlassov, KTH Royal Institute of Technology, Sweden Program Co-Chairs Lina Yao, University of New South Wales, Australia Hongzhi Yin, The University of Queensland, Australia Weiqing Wang, Monash University, Australia Workshop Chairs Muhammad Ali Babar, University of Adelaide, Australia Jian Cao, Shanghai Jiaotong University, China Rafael Tolosana, University of Zaragoza, Spain

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4th Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2018) at SC18: Extended abstracts due Aug. 15
by Jason D. Bakos 07 Aug '18

07 Aug '18

========================================================================== ** Call for Papers ** ========================================================================== Fourth International Workshop on Heterogeneous High-performance Reconfigurable Computing (H^2RC) ========================================================================== Held in conjunction with Supercomputing 2018 Sunday Morning, November 11, 2018 Dallas, TX http://h2rc.cse.sc.edu ========================================================================== Submission Deadline: August 15, 2018 (1 to 4 page extended abstracts) ========================================================================== As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier to use high-level programming models for FPGAs. Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now its fourth year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on how newly-available high-level programming models, including OpenCL, are already empowering HPC software developers to directly leverage FPGAs, and to identify future opportunities and needs for research in this area. ========================================================================== Topics ========================================================================== Submissions are solicited that explore the state of the art in the use of FPGAs in heterogeneous high-performance compute architectures and, at a system level, in data centers and supercomputers. FPGAs may be considered from either or both the distributed, parallel and composable fabric of compute elements or from their dynamic reconfigurability. We particularly encourage submissions which focus on the mapping of algorithms and applications to heterogeneous FPGA-based systems as well as the overall impact of such architectures on the compute capacity, cost, power efficiency, and overall computational capabilities of data centers and supercomputers. A non-comprehensive list of potential topics of interest is given below: 1. FPGAs in the cloud and data center 2. Cloud and data center applications 3. Leveraging reconfigurability 4. Benchmarks 5. Implementation studies 6. Programming languages, tools, and frameworks 7. Future-gazing 8. Community building ========================================================================== Special theme for 2018 ========================================================================== For this year's workshop we especially encourage the submission of papers on the topic of FPGA-based support for non-volatile memory and near-memory computing. Non-volatile memory (NVM) technologies such as Flash and Phase-Change memory potentially facilitate shared storage in the microsecond regime. In emerging systems, NVM may serve as a new level of memory hierarchy or as a networked resource. To this end, early work in developing both system-level interfaces to NVM (such as NVMe) and network-level interfaces to NVM (such as RDMA over Converged Ethernet 2) rely heavily on FPGAs as low-latency intermediaries. ========================================================================== Prospective authors are invited to submit relevant contributions as an extended abstract in ACM SIG Proceedings format of up to four pages. You can submit your contribution(s) through a link on the H2RC website: http://h2rc.cse.sc.edu The authors of accepted papers will be invited to present their work at the workshop. ========================================================================== Important dates: ========================================================================== Submission Deadline: August 15, 2018 Acceptance Notification: September 18, 2018 Camera-ready Manuscripts Due: October 15, 2018 Workshop Date: November 11, 2018 ========================================================================== Workshop Format: ========================================================================== H2RC is a half-day Sunday workshop. It will be comprised of: -- Keynote and invited talks -- Talks selected among paper submissions ========================================================================== Organizing Committee: ========================================================================== Michaela Blott, Xilinx Franck Cappello, Argonne National Lab Torsten Hoefler, ETH Zurich Jason D. Bakos, University of South Carolina ========================================================================== Technical Program Committee: ========================================================================== Rizwan Ashraf, Oak Ridge National Laboratory Paul Chow, University of Toronto Hans Eberle, NVIDIA Ken Eguro, Microsoft Research Xin Fang, Northeastern University Alan George, University of Pittsburgh Christoph Hagleitner, IBM Zheming Jin, Argonne National Lab Andreas Koch, TU Darmstadt Miriam Leeser, Northeastern University Chistian Plessl, University of Paderborn Viktor Prasanna, University of Southern California Marco Santambrogio, Politecnico Di Milano Yaman Umuroglu, Xilinx Research -- Jason D. Bakos, Ph.D. Professor Dept. of Computer Science and Engineering Univ. of South Carolina 301 Main St., Suite 3A01L Columbia, SC 29208 803-777-8627 (voice), 803-777-3767 (fax) http://www.cse.sc.edu/~jbakos jbakos(a)cse.sc.edu

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CFP: IEEE ISPA2018 (Parallel and Distributed Processing with Applications), Dec. 2018, Melbourne, Australia
by Jesson Butt 07 Aug '18

07 Aug '18

Call for papers: The 16th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2018), 11-13 Dec. 2018, Melbourne, Australia. Website: http://www.swinflow.org/confs/2018/ispa/ Key dates: Submission Deadline: August 31, 2018 (11:59pm UTC/GMT, firm) Notification: September 30, 2018 Final Manuscript Due: October 15, 2018 Submission site: http://www.swinflow.org/confs/2018/ispa/submission.htm Publication: Proceedings will be published by IEEE CS Press. Special issues: Distinguished papers will be selected for special issues in Information Sciences, Future Generation Computer Systems, Journal of Parallel and Distributed Computing, Concurrency and Computation: Practice and Experience =========== Introduction The IEEE ISPA 2018 (16th IEEE International Symposium on Parallel and Distributed Processing with Applications) is a forum for presenting leading work on parallel and distributed computing and networking, including architecture, compilers, runtime systems, applications, reliability, security, parallel programming models and much more. During the symposium, scientists and engineers in both academia and industry are invited to present their work on concurrent and parallel systems (multicore, multithreaded, heterogeneous, clustered systems, distributed systems, grids, clouds, and large scale machines). The 16th IEEE ISPA follows the tradition of previous successful IEEE ISPA conferences in the years from 2003 to 2017 in Asia, Europe, Australia and North America. It will feature sessions of regular presentations, workshops, tutorials and keynote speeches. IEEE ISPA 2018 is sponsored by the IEEE Technical Committee on Scalable Computing (TCSC) and the IEEE Computer Society. IEEE ISPA is particularly interested in research addressing heterogeneous computing with the use of accelerators, mobile computing, approximate computing, tools and methodologies to improve the quality of parallel programming and applying generic computing approaches to networks, in particular Software Defined networking and its applications. Scope and Topics *(1) Systems and Architectures Track* - Cloud computing and data center technology - Migration of computations - Multi-clouds environments, cloud federation, interoperability - Energy management and Green Computing - Wireless and mobile networks - Internet-Of-Things (IoT) - Social Networks, crowdsourcing, and P2P systems *(2) Technologies and Tools Track* - Building block processors: FPGA, multicore, GPU, NoC, SoC - Parallel and distributed algorithms - Tools/environments for parallel/distributed software development - Novel parallel programming paradigms - Programming models for cloud services and applications - Code generation and optimization - Compilers for parallel computers - Middleware and tools - Scheduling and resource management - Performance simulations, measurement, and evaluations - Reliability, fault tolerance, dependability, and security *(3) Applications Track* - High-performance scientific and engineering computing - Grid and cluster computing - Pervasive and ubiquitous computing - Databases, data mining, and data management - Big data and business analytics - Scientific cloud systems and services - Internet computing and web services - Application scenarios of IoT and ubiquitous computing - Experience with computational, workflow and data-intensive applications - Software Defined Networks and its applications Submission Guidelines Submissions must include an abstract, keywords, the e-mail address of the corresponding author and should not exceed 8 pages for main conference, including tables and figures in IEEE CS format. The template files for LATEX or WORD can be downloaded here. All paper submissions must represent original and unpublished work. Each submission will be peer reviewed by at least three program committee members. Submission of a paper should be regarded as an undertaking that, should the paper be accepted, at least one of the authors will register for the conference and present the work. Submit your paper(s) in PDF file at the submission site: http://www.swinflow.org/confs/2018/ispa/submission.htm. Publications Accepted and presented papers will be included into the IEEE Conference Proceedings published by IEEE CS Press. Authors of accepted papers, or at least one of them, are requested to register and present their work at the conference, otherwise their papers may be removed from the digital libraries of IEEE CS and EI after the conference. Distinguished papers will be selected for special issues in Information Sciences, Future Generation Computer Systems, Journal of Parallel and Distributed Computing, Concurrency and Computation: Practice and Experience. Honorary Chairs Wanlei Zhou, Deakin University, Australia Albert Zomaya, The University of Sydney, Australia General Chairs Geoffrey Fox, Indiana University, USA Beniamino Di Martino, Universita' della Campania "Luigi Vanvitelli", Italy Laurence Yang, St. Francis Xavier University, Canada Program Chairs Mianxiong Dong, Muroran Institute of Technology, Japan Rajiv Ranjan, Newcastle University, UK Massimo Cafaro, University of Salento, Lecce, Italy Workshop Chairs Young Choon Lee, Macquarie University, Australia Wei Zheng, Xiamen University, China

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