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Deadline extension: 3rd Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2017) at SC17: Extended abstracts due Sept. 15
by Jason D. Bakos 01 Sep '17

01 Sep '17

========================================================================== ** Call for Papers ** ========================================================================== Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2017) Held in conjunction with Supercomputing 2017 Friday Morning, November 17, 2017 Denver, CO http://h2rc.cse.sc.edu ========================================================================== Submission Deadline (EXTENDED): September 15, 2017 (one page extended abstracts) ========================================================================== As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier to use high-level programming models for FPGAs. Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its third year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on legacy and new high-level programming models, optimizations specific to scientific computing and data analytics, tools for performance/energy improvements, FPGA computing in the cloud, and popular applications for reconfigurable computing such as machine learning and big data. ========================================================================== Submissions (one page extended abstract): Submissions are solicited that explore the state of the art in the use of FPGAs in heterogeneous high-performance computing architectures and, at a system level, in data centers and supercomputers. FPGAs may be considered from either or both the distributed, parallel and composable fabric of compute elements or from their dynamic reconfigurability. We particularly encourage submissions which focus on the mapping of algorithms and applications to heterogeneous FPGA-based systems as well as the overall impact of such architectures on the compute capacity, cost, power efficiency, and overall computational capabilities of data centers and supercomputers. Submissions may report on theoretical or applied research, implementation case studies, benchmarks, standards, or any other area that promises to make a significant contribution to our understanding of heterogeneous high-performance reconfigurable computing and will help to shape future research and implementations in this domain. A non-comprehensive list of potential topics of interest is given below: 1. FPGAs in Supercomputer, Cloud and Data Center: FPGAs in relation to challenges to Cloud/Data Center/Supercomputing posed by the end of Dennard scaling 2. Supercomputing, Cloud and Data Center Applications: Exploiting FPGA compute fabric to implement critical cloud/HPC applications 3. Leveraging Reconfigurability: Using reconfigurability for new approaches to algorithms used in cloud/HPC applications 4. Benchmarks: Compute performance and/or power and cost efficiency for cloud/HPC with heterogeneous architectures using FPGAs 5. Implementation Studies: Heterogenous Hardware and Management Infrastructure 6. Programming Languages/Runtimes/OS/Tools/Frameworks for Heterogeneous High Performance Reconfigurable Computing 7. Future-gazing: New Applications/The Cloud Enabled by Heterogeneous High Performance Reconfigurable Computing, Evolution of Computer Architecture in relation to Heterogeneous High Performance Reconfigurable Computing 8. Community building: Standards, consortium activity, open source, education, initiatives to enable and grow Heterogeneous High Performance Reconfigurable Computing Prospective authors are invited to submit original and unpublished contributions as a ONE PAGE EXTENDED ABSTRACT in ACM SIG Proceedings format. ========================================================================== You can submit your contribution(s) through a link on the H2RC website: http://h2rc.cse.sc.edu ========================================================================== Important dates: Submission Deadline (extended): September 15, 2017 Acceptance Notification: October 15, 2017 Camera-ready Manuscripts Due: November 4, 2017 Workshop Date: November 17, 2017 ========================================================================== Workshop Format: H2RC is a half-day Friday workshop. It will be comprised of Keynote and invited talks and talks selected from paper submissions. Preliminary Agenda: 8:30 a.m. Opening Remarks 8:35 a.m. Keynote 1: FPGAs in AWS and First Use Cases (joint talk by AWS, Ngcodc and Xilinx) 9:35 a.m. Lightning Talks 10:00 a.m. Coffee break 10:30 a.m. Keynote 2: Brainwave (Microsoft Research) 11:30 p.m. Lightning talks 12:00 p.m. Invited talk 12:30 p.m. Adjorn ========================================================================== Organizing Committee: Workshop Organizers: Michaela Blott, Xilinx Franck Cappello, Argonne National Lab Torsten Hoefler, ETH Zurich Jason D. Bakos, University of South Carolina Program Committee: Rizwan Ashraf, Oak Ridge National Laboratory Paul Chow, University of Toronto Hans Eberle, NVIDIA Alan George, University of Florida Christoph Hagleitner, IBM Miriam Leeser, Northeastern University Viktor Prasanna, Univ. of Southern California Marco Santambrogio, Politecnico Di Milano Jeffrey Vetter, Oak Ridge National Lab -- Jason D. Bakos, Ph.D. Professor Dept. of Computer Science and Engineering Univ. of South Carolina 301 Main St., Suite 3A01L Columbia, SC 29208 803-777-8627 (voice), 803-777-3767 (fax) http://www.cse.sc.edu/~jbakos jbakos(a)cse.sc.edu

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Call For Papers [Extended Deadline]: ESPM2@SC17 - Third International Workshop on Extreme Scale Programming Models and Middleware
by Hari Subramoni 01 Sep '17

01 Sep '17

======================================================================== Call For Papers Third International IEEE Workshop on Extreme Scale Programming Models and Middleware (ESPM2 2017) November 12, 2017, Denver, Colorado to be held in conjunction with SuperComputing 2017, November 12 - 16, 2017 Denver, Colorado http://nowlab.cse.ohio-state.edu/espm2/ ======================================================================== Based on requests from authors, we have extended the technical paper submission deadline for ESPM2'17 to 09/11/17. A complete and updated "Call for Papers" follows. Next generation architectures and systems being deployed are characterized by high concurrency, low memory per-core, and multiple levels of hierarchy and heterogeneity. These characteristics bring out new challenges in energy efficiency, fault-tolerance and, scalability. It is commonly believed that software has the biggest share of the responsibility to tackle these challenges. In other words, this responsibility is delegated to the next generation programming models and their associated middleware/runtimes. This workshop focuses on different aspects of programming models such as task-based parallelism (Charm++, OCR, Habanero, Legion, X10, HPX, etc), PGAS (OpenSHMEM, UPC, CAF, Chapel, UPC++, etc.), BigData (Hadoop, Spark, etc), Deep Learning (Caffe, Microsoft CNTK, Google TensorFlow), directive-based languages (OpenMP, OpenACC) and Hybrid MPI+X, etc. It also focuses on their associated middleware (unified runtimes, interoperability for hybrid programming, tight integration of MPI+X, and support for accelerators) for next generation systems and architectures. The ultimate objective of the ESPM2 workshop is to serve as a forum that brings together researchers from academia and industry working in the areas of programming models, runtime systems, compilers, programming languages, and application developers. ESPM2 2017 will be held as a full day workshop in conjunction with the SuperComputing (SC 2017), Denver, Colorado, USA, Sunday, November 12th, 2017. Topics ------ ESPM2 2017 welcomes original submissions in a range of areas, including but not limited to: * New programming models, languages and constructs for exploiting high concurrency and heterogeneity * Experience with and improvements for existing parallel languages and run-time environments such as: - MPI - PGAS (OpenSHMEM, UPC, CAF, Chapel, UPC++, etc.) - Directive-based programming (OpenMP, OpenACC) - Asynchronous Task-based models (Charm++, OCR, Habanero, Legion, X10, HPX, etc) - Hybrid MPI+X models - BigData (Hadoop, Spark, etc), and - Deep Learning (Caffe, Microsoft CNTK, Google TensorFlow) * Parallel compilers, programming tools, and environments * Software and system support for extreme scalability including fault tolerance * Programming environments for heterogeneous multi-core systems and accelerators such as KNL, OpenPOWER, ARM, GPUs, FPGAs, MICs, and DSPs Papers should present original research and should provide sufficient background material to make them accessible to the broader community. Best Paper Award ---------------- Intel has generously offered to sponsor the Best Paper Award. This award will be given to the author(s) of the paper selected by the Technical Program Committee and the Program Chairs. The award will be determined from viewpoints of the technical and scientific merits, impact on the science and engineering of the research work and the clarity of presentation of the research contents in the paper. Keynote Speakers ---------------- We are happy to announce that Prof. William D. Gropp, Interim Director and Chief Scientist at the National Center for Supercomputing Applications and the Thomas M. Siebel Chair in Computer Science at the University of Illinois Urbana-Champaign will deliver the keynote address at ESPM2'17. Panel Information ----------------- Panel Topic : Effective Programming Models for Deep Learning at Scale Panel Moderator : Daniel Holmes, EPCC, The University of Edinburgh, UK. Panel Members : Coming soon! Paper Submission and Registration --------------------------------- Abstracts and papers need to be submitted via the EasyChair conference system. EasyChair URL for ESPM2'17: https://easychair.org/conferences/?conf=espm22017 Submissions should not exceed 8 pages using ACM format with 10pt font. Each submission must be a single PDF file. Papers must be submitted in PDF format (readable by Adobe Acrobat Reader 5.0 and higher) and formatted for 8.5" x 11" (U.S. Letter). The manuscript should be formatted according to ACM format (see http://www.acm.org/sigs/publications/proceedings-templates) Papers should present original research and should provide sufficient background material to make them accessible to the broader community. It should not be submitted in parallel to any other conference or journal. At least one of the authors of each accepted paper must register as a participant of the workshop and present the paper at the workshop, in order to have the paper published in the proceedings. Each research paper will be taken through a comprehensive peer review process by an internationally recognized group of experts in the field. Papers will be evaluated along the metrics of a) Quality of Presentation; b) Novelty / Originality; c) Relation to State of the Art; d) Technical Strength; e) Significance of Work; and f) Relevance to Workshop. Every effort will be made to ensure that each paper receives multiple reviews. Please contact the Program Chairs for any questions/clarifications Proceedings Information ----------------------- ACM SigHPC will publish the workshop proceedings which will be available through the ACM Digital Library. The camera-ready versions need to be submitted via the EasyChair conference management system. The link to the submission site will be provided soon. Please contact the Program Chairs for any questions/clarifications. Important Dates --------------- Technical paper submission deadline : 11:59 PM, AoE, September 11, 2017 Author notification : October 7, 2017 Camera-ready deadline : 11:59 PM, AoE, October 13, 2017 Workshop : Sunday, November 12, 2017 ESPM2'17 Workshop Organizers ---------------------------- Hari Subramoni, The Ohio State University Karl Schulz, Intel Corporation Dhabaleswar K. (DK) Panda, The Ohio State University Program Committee ----------------- * Guang R. Gao, University of Delaware * Vladimir Getov, University of Westminster, UK * Jeff Hammond, Intel Labs * Michael A. Heroux, Sandia National Laboratories * Costin Iancu, Lawrence Berkeley National Laboratory * Darren Kerbyson, Pacific Northwest National Laboratory * Guangming Tan, Institute of Computing Technology, Chinese Academy of Sciences, China * Olivier Tardieu, IBM T.J. Watson Research Center * Daniel Tian, The Portland Group * Sean Treichler, NVIDIA Corporation * Abhinav Vishnu, Pacific Northwest National Laboratory Further Information ------------------- See the ESPM2'17 website at http://nowlab.cse.ohio-state.edu/espm2/ Thanks, The ESPM2'17 Organizing Committee.

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JSC Special Issue on Dynamic Geometry and Automated Reasoning - Deadline Extension
by Francisco Botana 31 Aug '17

31 Aug '17

Please help us disseminating this announcement. Sorry for duplicates. ===================== DEADLINE EXTENSION: Due to the concurrence, in this coming month of September 2017, of several call for papers for different journals and conference proceedings, on topics related to automated reasoning, symbolic computation and dynamic geometry, we have considered extending substantially the deadline for our JSC Special Issue on Dynamic Geometry and Automated Reasoning. Please notice the new submission deadline of February 2018! Further details follow: *** CALL FOR PAPERS *** Journal of Symbolic Computation* https://www.journals. elsevier.com/journal-of-symbolic-computation <http://elsevier.com/journal-of-symbolic-computation> Call for contributions to the Special Issue on Dynamic Geometry and Automated Reasoning https://sites.google.com/site/kovzol/jsc-si-dg-ar GUEST EDITORS: Francisco Botana, University of Vigo, Spain Zoltán Kovács, The Private University College of Education of the Diocese of Linz, Austria Tomas Recio, University of Cantabria, Spain IMPORTANT DATES (EXTENDED) * submission deadline: February 1, 2018 * notification of acceptance / rejection: July 1, 2018 * final versions: September 15, 2018 SCOPE: Since the last half century, automated deduction in elementary geometry has become one of the most successful achievements in the field of automated reasoning. Along these decades various methods and techniques have been studied and developed for automated proving and discovering of elementary geometry statements. On the other hand, dynamic geometry software systems have emerged, such as Cabri Geometry, C.a.R., Cinderella, DrGeo, GeoGebra, The Geometer's Sketchpad, Geometry Expert, Geometry Expressions or Kig with an ever-increasing presence in mathematics education. Some of them possess a large number of users (over thirty million) all around the world. The merging of these two tools (automatic proving and dynamic geometry) is, thus, a very natural, challenging and promising issue, currently involving logic, symbolic computation, software development, algebraic geometry and mathematics education experts all from over the world. The Special Issue intends to be an opportunity for - presenting the current state of the art concerning the development of automatic proving features on dynamic geometry systems, - discussing the current and potential applications of such features in different contexts, such as CAGD or mathematics education. TOPICS (not restricted to): - Algorithmic aspects: formal, logic and algebraic geometry approaches, constraint solving, invariant and coordinate-free methods, real and complex geometry issues, probabilistic, synthetic approaches, techniques from discrete mathematics, combinatorics, and numerics. - Software aspects: Implementation of automated proving methods in dynamic geometry programs, design of packages and systems, data representation. Parallel and distributed computing, considerations for modern hardware and new devices. User-interface issues, use with systems for digital libraries, courseware, ... - Application aspects: applications to mechanics, geometric modeling, CAGD/CAD, computer vision, robotics and education. Papers must not duplicate work already published or submitted for publication elsewhere. All the papers will be refereed according to the JSC standards. Papers should follow the guidelines for JSC submissions (see https://www.elsevier.com/journals/journal-of-symbolic-computation/0747-7171…), and should be submitted through Easychair (https://easychair.org/conferences/?conf=jscdgarsi2018). The introduction of the paper must explicitly address the following questions in succinct and informal manner: - What is the problem? - Why is the problem important? - What has been done so far on the problem? - What is the main contribution of the paper on the problem? - Why is the contribution original? (see below for clarification) - Why is the contribution non-trivial? Make the paper complete (since there is no page limit): - All the related works and issues must be completely and carefully discussed. - All the previous relevant JSC papers must be properly cited and discussed. - All the theorems must be rigorously proved (no sketch allowed). - All the important definitions/theorems/algorithms must be illustrated by well-chosen examples. * An international journal, the Journal of Symbolic Computation, founded by Bruno Buchberger in 1985, is directed to mathematicians and computer scientists who have a particular interest in symbolic computation. Automated theorem proving is one of the research areas of interest highlighted in the Journal’s description. The Journal of Symbolic Computation has a 1.274 Impact Factor, according to the last Thompson Reuters Journal Citation Reports (Clarivate Analytics, 2017).

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Deadline extension: CFP Journal Symbolic Computation Special Issue on Dynamic Geometry and Automated Reasoning
by Prof. Tomas Recio 30 Aug '17

30 Aug '17

Please help us disseminating this announcement. Sorry for duplicates. ===================== DEADLINE EXTENSION: Due to the concurrence, in this coming month of September 2017, of several call for papers for different journals and conference proceedings, on topics related to automated reasoning, symbolic computation and dynamic geometry, we have considered extending substantially the deadline for our JSC Special Issue on Dynamic Geometry and Automated Reasoning. Please notice the new submission deadline of February 2018! Further details follow: *** CALL FOR PAPERS *** Journal of Symbolic Computation* https://www.journals <https://www.journals/>. elsevier.com/journal-of-symbolic-computation <http://elsevier.com/journal-of-symbolic-computation> Call for contributions to the Special Issue on Dynamic Geometry and Automated Reasoning https://sites.google.com/site/kovzol/jsc-si-dg-ar <https://sites.google.com/site/kovzol/jsc-si-dg-ar> GUEST EDITORS: Francisco Botana, University of Vigo, Spain Zoltán Kovács, The Private University College of Education of the Diocese of Linz, Austria Tomas Recio, University of Cantabria, Spain IMPORTANT DATES (EXTENDED) submission deadline: February 1, 2018 notification of acceptance / rejection: July 1, 2018 final versions: September 15, 2018 SCOPE: Since the last half century, automated deduction in elementary geometry has become one of the most successful achievements in the field of automated reasoning. Along these decades various methods and techniques have been studied and developed for automated proving and discovering of elementary geometry statements. On the other hand, dynamic geometry software systems have emerged, such as Cabri Geometry, C.a.R., Cinderella, DrGeo, GeoGebra, The Geometer's Sketchpad, Geometry Expert, Geometry Expressions or Kig with an ever-increasing presence in mathematics education. Some of them possess a large number of users (over thirty million) all around the world. The merging of these two tools (automatic proving and dynamic geometry) is, thus, a very natural, challenging and promising issue, currently involving logic, symbolic computation, software development, algebraic geometry and mathematics education experts all from over the world. The Special Issue intends to be an opportunity for - presenting the current state of the art concerning the development of automatic proving features on dynamic geometry systems, - discussing the current and potential applications of such features in different contexts, such as CAGD or mathematics education. TOPICS (not restricted to): - Algorithmic aspects: formal, logic and algebraic geometry approaches, constraint solving, invariant and coordinate-free methods, real and complex geometry issues, probabilistic, synthetic approaches, techniques from discrete mathematics, combinatorics, and numerics. - Software aspects: Implementation of automated proving methods in dynamic geometry programs, design of packages and systems, data representation. Parallel and distributed computing, considerations for modern hardware and new devices. User-interface issues, use with systems for digital libraries, courseware, ... - Application aspects: applications to mechanics, geometric modeling, CAGD/CAD, computer vision, robotics and education. Papers must not duplicate work already published or submitted for publication elsewhere. All the papers will be refereed according to the JSC standards. Papers should follow the guidelines for JSC submissions (see https://www.elsevier.com/journals/journal-of-symbolic-computation/0747-7171… <https://www.elsevier.com/journals/journal-of-symbolic-computation/0747-7171…>), and should be submitted through Easychair (https://easychair.org/conferences/?conf=jscdgarsi2018 <https://easychair.org/conferences/?conf=jscdgarsi2018>). The introduction of the paper must explicitly address the following questions in succinct and informal manner: - What is the problem? - Why is the problem important? - What has been done so far on the problem? - What is the main contribution of the paper on the problem? - Why is the contribution original? (see below for clarification) - Why is the contribution non-trivial? Make the paper complete (since there is no page limit): - All the related works and issues must be completely and carefully discussed. - All the previous relevant JSC papers must be properly cited and discussed. - All the theorems must be rigorously proved (no sketch allowed). - All the important definitions/theorems/algorithms must be illustrated by well-chosen examples. * An international journal, the Journal of Symbolic Computation, founded by Bruno Buchberger in 1985, is directed to mathematicians and computer scientists who have a particular interest in symbolic computation. Automated theorem proving is one of the research areas of interest highlighted in the Journal’s description. The Journal of Symbolic Computation has a 1.274 Impact Factor, according to the last Thompson Reuters Journal Citation Reports (Clarivate Analytics, 2017).

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ESORICS 2017: Call for Participation
by Cristina Alcaraz 29 Aug '17

29 Aug '17

============================================================================== ESORICS 2017: CALL FOR PARTICIPATION 22nd European Symposium on Research in Computer Security Oslo, Norway — September 11-15, 2017 ============================================================================== WWW: https://www.ntnu.edu/web/esorics2017/ Overview ------------------------------------ ESORICS is the annual European research event in Computer Security. The Symposium started in 1990 and has been held in several European countries, attracting a wide international audience from both the academic and industrial communities. The 22nd European Symposium on Research in Computer Security (ESORICS 2017) will be held in Oslo, Norway. ESORICS 2017 spans a total of 3 days, featuring: * 3 keynote speeches (Cormac Herley, Paul Syverson, Sandro Etalle) * 54 paper presentations in 3 days (Sep 11-13) * 8 workshops (Sept 14 - 15) Presentations Program ------------------------------------ The 54 papers of ESORICS 2017 are distributed between **18 sessions** in **two parallel tracks**. Following is the list of paper presentations for the main ESORICS conference. For the workshop programs, please consult their corresponding websites: * SECPRE 2017: https://samosweb.aegean.gr/secpre2017/ * SecSE 2017: http://secse.org * CBT 2017: http://www.deic.uab.cat/~jherrera/CBT/ * DPM 2017: http://deic.uab.cat/conferences/dpm/dpm2017/ * STM 2017: http://stm2017.di.unimi.it * QASA 2017: http://www.iit.cnr.it/qasa2017/ * CyberICPS: http://www.ds.unipi.gr/cybericps2017/ * SIoT 2017: http://siot-workshop.org ### September 11 - Day 1 ########### 09:30 - 10:30 * Keynote: Cormac Herley - Justifying Security Measures - a Position Paper 11:00 - 12:30 * Session 1: Security of embedded things - Shortfall-based Optimal Placement of Security Resources for Mobile IoT Scenarios Antonino Rullo, Edoardo Serra, Elisa Bertino and Jorge Lobo - Analyzing the Capabilities of the CAN Attacker Sibylle Froeschle and Alexander Stühring - Boot Attestation: Secure Remote Reporting with Off-The-Shelf IoT Sensors Steffen Schulz, André Schaller, Florian Kohnhäuser, and Stefan Katzenbeisser * Session 2: Cryptographic Application I - Per-Session Security: Password-Based Cryptography Revisited Gregory Demay, Peter Gazi, Ueli Maurer and Björn Tackmann - Non-Interactive Provably Secure Attestations for Arbitrary RSA Prime Generation Algorithm Fabrice Benhamouda, Houda Ferradi, Rémi Géraud and David Naccache - Tightly Secure Ring-LWE Based Key Encapsulation with Short Ciphertexts Martin Albrecht, Emmanuela Orsini, Kenneth Paterson, Guy Peer and Nigel Smart 14:00 - 15:30 * Session 3: Documents and Authorship - Identifying Multiple Authors in a Binary Program Xiaozhu Meng, Barton Miller and Kwang-Sung Jun - Verifiable Document Redacting Herve Chabanne, Rodolphe Hugel and Julien Keuffer - Source Code Authorship Attribution using Long Short-Term Memory Based Networks Bander Alsulami, Edwin Dauber, Richard Harang, Spiros Mancoridis and Rachel Greenstadt * Session 4: Analysis of Security Protocols - Automated analysis of equivalence properties for security protocols using else branches Ivan Gazeau and Steve Kremer and Levente Buttyán - Secure Authentication in the Grid: A formal analysis of DNP3: SAv5 Cas Cremers, Martin Dehnel-Wild and Kevin Milner - Modular Verification of Protocol Equivalence in the Presence of Randomness Matthew Bauer, Rohit Chadha and Mahesh Viswanathan 16:00 - 17:30 * Session 5: Threat Analysis - Preventing Advanced Persistent Threats in Complex Control Networks Juan E. Rubio, Cristina Alcaraz and Javier Lopez - MTD CBITS: Moving Target Defense for Cloud-Based IT Systems Alexandru G. Bardas, Sathya C. Sundaramurthy, Xinming Ou and Scott A. Deloach - Is my attack tree correct? Maxime Audinot, Sophie Pinchinat and Barbara Kordy * Session 6: Side Channels and data leakage - On-Demand Time Blurring to Support Side-Channel Defense Weijie Liu, Debin Gao and Mike Reiter - Acoustic Data Exfiltration from Speakerless Air-Gapped Computers via Covert Hard-Drive Noise Mordechai Guri, Yosef Solewicz, Andrey Daidakulov and Yuval Elovici - Practical Keystroke Timing Attacks in Sandboxed JavaScript Moritz Lipp, Daniel Gruss, Michael Schwarz, David Bidner, Clémentine Maurice and Stefan Mangard ### September 12 - Day 2 ########### 09:00 - 10:00 * Keynote: Paul Syverson - The Once and Future Onion 10:30 - 12:00 * Session 7: Vulnerabilities and Malware - Mirage: Toward a Stealthier and Modular Malware Analysis Sandbox for Android Lorenzo Bordoni, Mauro Conti and Riccardo Spolaor - VuRLE: Automatic Vulnerability Detection and Repair by Learning from Examples Siqi Ma, Ferdian Thung, David Lo, Cong Sun and Robert Deng - Adversarial Examples for Malware Detection Kathrin Grosse, Nicolas Papernot, Praveen Manoharan, Backes Michael and Patrick McDaniel Russo * Session 8: Privacy in Systems - PerfWeb: How to Violate Web Privacy with Hardware Performance Events Berk Gulmezoglu, Andreas Zankl, Thomas Eisenbarth and Berk Sunar - SePCAR: A Secure and Privacy-enhancing Protocol for Car Access Provision Iraklis Symeonidis, Abdelrahaman Aly, Mustafa Asan Mustafa, Bart Mennink, Siemen Dhooghe and Bart Preneel - Privacy Implications of Room Climate Data Philipp Morgner, Christian Müller, Matthias Ring, Björn Eskofier, Christian Riess, Frederik Armknecht and Zinaida Benenson 13:30 - 15:00 * Session 9: Network security - Link-Layer Device Type Classification on Encrypted Wireless Traffic with COTS Radios Rajib Ranjan Maiti, Sandra Siby, Ragav Sridharan and Nils Ole Tippenhauer - Preventing DNS amplification attacks using the history of DNS queries with SDN Soyoung Kim, Sora Lee, Geumhwan Cho, Muhammad Ejaz Ahmed, Jaehoon Paul Jeong and Hyoungshick Kim - Zero Round-Trip Time for the Extended Access Control Protocol Jacqueline Brendel and Marc Fischlin * Session 10: Controlling Access - No sugar but all the taste! Memory Encryption without Architectural Support Panagiotis Papadopoulos, George Christou, Giorgos Vasiliadis, Evangelos Markatos and Sotiris Ioannidis - Tree-based Cryptographic Access Control James Alderman, Naomi Farley and Jason Crampton - Securing Data Analytics on SGX With Randomization Swarup Chandra, Vishal Karande, Zhiqiang Lin, Latifur Khan, Murat Kantarcioglu and Bhavani Thuraisingham 15:30 - 17:00 * Session 11: Information Flow - We are Family: Relating Information-Flow Trackers Musard Balliu, Daniel Schoepe and Andrei Sabelfeld - A Better Composition Operator for Quantitative Information Flow Analyses Kai Engelhardt - WebPol: Fine-grained Information Flow Policies for Web Browsers Abhishek Bichhawat, Vineet Rajani, Jinank Jain, Deepak Garg and Christian Hammer * Session 12: Blockchain and social networks - A Traceability Analysis of Monero’s Blockchain Amrit Kumar, Clément Fischer, Shruti Tople and Prateek Saxena -RingCT 2.0: A Compact Linkable Ring Signature Based Protocol for Blockchain Cryptocurrency Monero Shi-Feng Sun, Man Ho Au, Joseph Liu and Tsz Hon Yuen - Secure Computation in Online Social Networks Foteini Baldimtsi, Dimitrios Papadopoulos, Stavros Papadopoulos, Alessandra Scafuro and Nikos Triandopoulos ### September 13 - Day 3 ########### 09:00 - 10:00 * Keynote: Sandro Etalle - From Intrusion Detection to Software Design 10:30 - 12:30 * Session 13: Web Security - DeltaPhish: Detecting Phishing Webpages in Compromised Websites Igino Corona, Battista Biggio, Matteo Contini, Luca Piras, Roberto Corda, Mauro Mereu, Guido Mureddu, Davide Ariu and Fabio Roli - DOMPurify: Client-Side Protection against XSS and Markup Injection Mario Heiderich, Christopher Späth, and Jörg Schwenk - Quantifying Web Adblocker Privacy Arthur Gervais, Alexandros Filios, Vincent Lenders and Srdjan Capkun * Session 14: Cryptographic signatures - Reusing Nonces in Schnorr Signatures Marc Beunardeau, Aisling Connolly, Remi Geraud, David Naccache and Damien Vergnaud - How to Circumvent the Structure-Preserving Signatures Lower Bounds MEssam Ghadafi - Server-Supported RSA Signatures for Mobile Devices Ahto Buldas, Aivo Kalu, Peeter Laud and Mart Oruaas 13:30 - 15:00 * Session 15: Formal techniques - Inference-Proof Updating of a Weakened View under the Modification of Input Parameters Joachim Biskup and Marcel Preuß - Verifying Constant-Time Implementations by Abstract Interpretation Sandrine Blazy, David Pichardie and Alix Trieu - AVR Processors as a Platform for Language-Based Security Florian Dewald, Heiko Mantel and Alexandra Weber * Session 16: Privacy and garbled circuits - Labeled Homomorphic Encryption: Scalable and Privacy-Preserving Processing of Outsourced Data Manuel Barbosa, Dario Catalano and Dario Fiore - New Way for Privacy-Preserving Decision Tree Evaluation Raymond K. H. Tai, Jack P. K. Ma, Yongjun Zhao and Sherman S. M. Chow - Enforcing Input Correctness via Certification in Garbled Circuit Evaluation Yihua Zhang, Marina Blanton and Fattaneh Bayatbabolghani 15:30 - 17:00 * Session 17: Intrusion Detection - Secure IDS Offloading with Nested Virtualization and Deep VM Introspection Shohei Miyama and Kenichi Kourai - Network Intrusion Detection based on Semi-Supervised Variational Auto-Encoder Genki Osada, Kazumasa Omote and Takashi Nishide - LeaPS: Learning-Based Proactive Security Auditing for Clouds Suryadipta Majumdar, Yosr Jarraya, Momen Oqaily, Amir Alimohammadifar, Makan Pourzandi, Lingyu Wang and Mourad Debbabi * Session 18: Cryptographic Applications II - Multiple Rate Threshold FlipThem David Leslie, Chris Sherfield and Nigel Smart - Stringer: Measuring the Importance of Static Data Comparisons to Detect Backdoors and Undocumented Functionality Sam L. Thomas, Tom Chothia and Flavio D. Garcia - Generic Constructions for Fully Secure Revocable Attribute-Based Encryption Kotoko Yamada, Nuttapong Attrapadung, Keita Emura, Goichiro Hanaoka and Keisuke Tanaka

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Cyber Security PhD Scholarship – The University of Newcastle with the Defense Science and Technology (DST) Group
by Vijay Varadharajan 29 Aug '17

29 Aug '17

Cyber Security PhD Scholarship – The University of Newcastle with the Defense Science and Technology (DST) Group Supervisors: Prof. Vijay Varadharajan, The University of Newcastle and Dr. Anton V. Uzunov, DST Group Topic Area: Advanced Authorization Infrastructures for Distributed Autonomic Systems Autonomic computing – or equivalently, self-adaptive computing – is concerned with supporting dynamic system evolution in response to changing internal or external circumstances, by endowing systems with automated self-management capabilities, thereby turning ordinary software systems into autonomic systems (or equivalently, self-adaptive or self-managing systems). One of the core properties whose enforcement leads to supporting such self-management capabilities is self-protection, which can be defined as a system’s ability to anticipate, to prevent, to detect and guard itself against cyber security threats. A significant problem with self-protection is how to constrain and control system actions, which involves aspects such as specification of privileges to perform actions, propagation of privileges in a distributed environment and their enforcement in heterogeneous systems and devices, ranging from cloud servers to mobile Internet of Things. The project is expected to investigate cryptographically enforced access control models and distributed capability-based models. The research will consider how access classes and capabilities with different privileges can be specified, keys and capabilities can be securely propagated in distributed, heterogeneous environments, how access to services and to devices/nodes should be enforced in a decentralized context, and what adaptation mechanisms should be applied in response to changing system/operational conditions. The project will involve the design of security architecture, development of new algorithms as well as the development of proof-of-concept implementations or case studies to validate the developed models and techniques in simulated or real-life scenarios. It is envisioned that the outcomes and outputs of the project will be specifically applicable to both IoT and autonomous cyber defense scenarios, and all case studies and/or application examples will be drawn from these areas. Scholarship Duration: 3 and 1/2 years Eligibility * Australian Citizenship required. * Must be Motivated and Committed to Doing Research * Knowledge of Cryptography and Security Techniques will be helpful. Contact: vijay.varadharajan(a)newcastle.edu.au<mailto:vijay.varadharajan@newcastle.edu.au> or Anton.Uzunov(a)dst.defence.gov.au<mailto:Anton.Uzunov@dst.defence.gov.au>

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Research Fellow Position in Software Defined Networks Security at Advanced Cyber Security Engineering Research Centre, The University of Newcastle
by Vijay Varadharajan 29 Aug '17

29 Aug '17

Research Fellow Position in Software Defined Networks Security at the Advanced Cyber Security Engineering Research Centre, The University of Newcastle A post doc Research Fellow position on Software Defined Networks (SDN) Security is available at the Advanced Cyber Security Engineering Research Centre. This position is funded by the Defence Science and Technology Group and it involves research and development in SDN Security. The Research Fellow is expected to work in the design and implementation of security architectures for SDN network services. Work will involve the design and implementation of security policies across distributed SDN domains under different management authorities. The Research Fellow is expected to work in the development of a Policy based Security Application at the SDN Controller and in the specification and management of security policies for provision of services across multiple autonomous domains. Programming and implementation experience is required as well as the ability to design network systems. In particular, experience python and java programming would be required. Background and expertise in security, especially systems and network security is highly desirable. Experience in writing good quality research papers is also necessary. The position is available immediately. Please send your expression of interest describing why you would be suitable for this position and attach your CV as well as your research and implementation experience in network systems and security. Start Date: The starting date of the position is immediate. Duration: Initially the Fellowship is for 1 year. There is potential for the Fellowship to be extended further subject to funding. Salary will be at the academic pay scale Level A Step 6. Contact Details: For further information, please contact Professor Vijay Varadharajan, Global Innovation Chair Professor in Cyber Security, vijay.varadharajan(a)newcastle.edu.au<mailto:vijay.varadharajan@newcastle.edu.au>, Tel: +61 2 4921 8687

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Call For Papers: The 1st International Workshop on Big Data Analytic for Cyber Crime Investigation and Prevention
by Andrii Shalaginov 28 Aug '17

28 Aug '17

Dear Colleague, (Apologies for multiple postings) We would like to invite you to submit your contributions to the 1st International Workshop on Big Data Analytic for Cyber Crime Investigation and Prevention. It is co-located with IEEE International Conference on Big Data 2017 that will take place in Boston, USA, December 11-14, 2017. Workshop webpage: https://www.ntnu.edu/iik/digital_forensics/ieeebigdata2017 *** IMPORTANT DATES *** Sept 10, 2017: Due date for full workshop papers submission Oct 15, 2017: Notification of paper acceptance to authors Nov 15, 2017: Camera-ready for accepted papers Dec 11-14, 2017: Workshop *** INTRODUCTION *** The big data paradigm has become inevitable in every aspect of the digital forensics process. Increase in personal devices (such as computers, smart phones, tablets, sensors and storage mediums) results in an expanding volume of potential evidence found in them. The increase in data is one of the largest challenges facing law enforcements’ timely prosecutions; with the effect, that human analysts can no longer be the lone actor in the loop. There is a need to create innovative and advanced models and analysis methods to help human analysts within law enforcements in order to automatically aid with the discovery, correlation, examination, analysis and understanding of evidence in criminal cases. Advanced big data analytics are important for cybercrime investigation and require novel approaches for automation. *** PROPOSED TOPICS *** Note that the topics are not limited to this proposed list. 1. Algorithms - Machine learning-aided analysis - Graph-based detection - Topic modeling - Secure platforms - Distributed storage and processing - Secure collaborative platforms 2. Applications - Network forensics readiness - Cyber threats intelligence - Malware analysis and detection - Emails mining - Events correlations - Access logs analysis - Mobile and Internet of Things forensics - Fraud detection - Database forensics 3. Data - Novel datasets - Digital forensics data simulation - Anonymised case data - Data storage standards - New formats and taxonomies *** PROGRAM CO-CHAIRS *** Andrii Shalaginov, Norwegian University of Science and Technology Katrin Franke, Norwegian University of Science and Technology Jan William Johnsen, Norwegian University of Science and Technology *** PROGRAM COMMITTEE *** Asif Iqbal (KTH Royal Institute of Technology) Bojan Kolosnjaji (Technical University of Munich) Carl Leichter (Norwegian University of Science and Technology) Dmitry Kangin (University of Exeter) Emiliano Casalicchio (Blekinge Institute of Technology) Ethan Rudd (University of Colorado Colorado Springs) Hamid Ebadi (Chalmers University of Technology) Hanno Langweg (Konstanz University of Applied Sciences) Heri Ramampiaro (Norwegian University of Science and Technology) Martin Boldt (Blekinge Institute of Technology) Michael McGuire (Towson University) Olaf M. Maennel (Tallinn University of Technology) Pavel Gladyshev (Dublin School of Computer Science) Pierre Lison (Norwegian Computing Centre) *** PAPER SUBMISSION *** Our workshop invites authors to submit: full-length papers (up to ten pages), short papers (up to six pages) or abstract papers (up to three pages) through the online submission system: https://wi-lab.com/cyberchair/2017/bigdata17/scripts/submitform.php?subarea… Papers have to follow the IEEE 2-column format and the Computer Society Proceedings Manuscript Formatting Guidelines. See formatting instructions here: https://www.ntnu.edu/iik/digital_forensics/ieee-bigdata-2017-formatting-ins… *** BEST PAPERS *** Selected papers are nominated for submission to “Special Issue on Cyber Threat Intelligence and Analytics”. Extended papers should have at least 60% of new material and will be sent through a review process to ensure the quality of contributions. *** CONTACTS*** If you have any questions, do not hesitate to contact Andrii Shalaginov (andrii.shalaginov(a)ntnu.no) and Jan William Johnsen (jan.w.johnsen(a)ntnu.no). Best regards, Andrii Shalaginov, on behalf of Katrin Franke and Jan William Johnsen Norwegian University of Science and Technology, Gjøvik, Norway

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CFP: 3rd Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2017) at SC17: Extended abstracts due Sept. 1
by Jason D. Bakos 25 Aug '17

25 Aug '17

========================================================================== ** Call for Papers ** ========================================================================== Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2017) Held in conjunction with Supercomputing 2017 Friday Morning, November 17, 2017 Denver, CO http://h2rc.cse.sc.edu ========================================================================== Submission Deadline: September 1, 2017 (one page extended abstracts) ========================================================================== As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier to use high-level programming models for FPGAs. Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its third year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on legacy and new high-level programming models, optimizations specific to scientific computing and data analytics, tools for performance/energy improvements, FPGA computing in the cloud, and popular applications for reconfigurable computing such as machine learning and big data. ========================================================================== Submissions (one page extended abstract): Submissions are solicited that explore the state of the art in the use of FPGAs in heterogeneous high-performance computing architectures and, at a system level, in data centers and supercomputers. FPGAs may be considered from either or both the distributed, parallel and composable fabric of compute elements or from their dynamic reconfigurability. We particularly encourage submissions which focus on the mapping of algorithms and applications to heterogeneous FPGA-based systems as well as the overall impact of such architectures on the compute capacity, cost, power efficiency, and overall computational capabilities of data centers and supercomputers. Submissions may report on theoretical or applied research, implementation case studies, benchmarks, standards, or any other area that promises to make a significant contribution to our understanding of heterogeneous high-performance reconfigurable computing and will help to shape future research and implementations in this domain. A non-comprehensive list of potential topics of interest is given below: 1. FPGAs in Supercomputer, Cloud and Data Center: FPGAs in relation to challenges to Cloud/Data Center/Supercomputing posed by the end of Dennard scaling 2. Supercomputing, Cloud and Data Center Applications: Exploiting FPGA compute fabric to implement critical cloud/HPC applications 3. Leveraging Reconfigurability: Using reconfigurability for new approaches to algorithms used in cloud/HPC applications 4. Benchmarks: Compute performance and/or power and cost efficiency for cloud/HPC with heterogeneous architectures using FPGAs 5. Implementation Studies: Heterogenous Hardware and Management Infrastructure 6. Programming Languages/Runtimes/OS/Tools/Frameworks for Heterogeneous High Performance Reconfigurable Computing 7. Future-gazing: New Applications/The Cloud Enabled by Heterogeneous High Performance Reconfigurable Computing, Evolution of Computer Architecture in relation to Heterogeneous High Performance Reconfigurable Computing 8. Community building: Standards, consortium activity, open source, education, initiatives to enable and grow Heterogeneous High Performance Reconfigurable Computing Prospective authors are invited to submit original and unpublished contributions as a ONE PAGE EXTENDED ABSTRACT in ACM SIG Proceedings format. ========================================================================== You can submit your contribution(s) through a link on the H2RC website: http://h2rc.cse.sc.edu ========================================================================== Important dates: Submission Deadline: September 1, 2017 Acceptance Notification: October 15, 2017 Camera-ready Manuscripts Due: November 4, 2017 Workshop Date: November 17, 2017 ========================================================================== Workshop Format: H2RC is a half-day Friday workshop. It will be comprised of Keynote and invited talks and talks selected from paper submissions. ========================================================================== Organizing Committee: Workshop Organizers: Michaela Blott, Xilinx Franck Cappello, Argonne National Lab Torsten Hoefler, ETH Zurich Jason D. Bakos, University of South Carolina Program Committee: Rizwan Ashraf, Oak Ridge National Laboratory Paul Chow, University of Toronto Carl Ebeling, Altera Hans Eberle, NVIDIA Alan George, University of Florida Christoph Hagleitner, IBM Miriam Leeser, Northeastern University Viktor Prasanna, Univ. of Southern California Marco Santambrogio, Politecnico Di Milano Jeffrey Vetter, Oak Ridge National Lab -- Jason D. Bakos, Ph.D. Professor Dept. of Computer Science and Engineering Univ. of South Carolina 301 Main St., Suite 3A01L Columbia, SC 29208 803-777-8627 (voice), 803-777-3767 (fax) http://www.cse.sc.edu/~jbakos jbakos(a)cse.sc.edu

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[CFP] IA^3 2017 - Deadline Extended!
by Tumeo, Antonino 23 Aug '17

23 Aug '17

[Apologies if you receive multiple copies of this CFP] NEWS: DEADLINE EXTENDED TO SEPTEMBER 7! IA^3 2017 Seventh Workshop on Irregular Applications: Architectures and Algorithms http://hpc.pnl.gov/IA3/ November 13, 2017 In conjunction with SC17 In collaboration with ACM SIGHPC Sponsored by IEEE TCHPC Call for Papers Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, tables, sparse matrices, deep nets, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers. Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years. This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to: * Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors * Network architectures and interconnect (including high-radix networks, optical interconnects) * Novel memory architectures and designs (including processors-in memory) * Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) * Modeling, simulation and evaluation of novel architectures with irregular workloads * Innovative algorithmic techniques * Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.) * Impact of irregularity on machine learning approaches * Parallelization techniques and data structures for irregular workloads * Data structures combining regular and irregular computations (e.g., attributed graphs) * Approaches for managing massive unstructured datasets (including streaming data) * Languages and programming models for irregular workloads * Library and runtime support for irregular workloads * Compiler and analysis techniques for irregular workloads * High performance data analytics applications, including graph databases Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation. Artifact Evaluation For this edition of IA^3, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation process, similarly to the process followed for SC17. The participation to the Artifact Evaluation process is voluntary and will not change decisions regarding the paper. However, papers that undergo the evaluation process will receive a seal of approval on the paper, and will be able to participate in the BEST PAPER AWARD selection. DIVIDITI will provide an Amazon Gift Voucher (valued $200) to the authors of the paper that passes artifact evaluation with the highest score and that shares the artifact in the CK (Collective Knowledge - https://github.com/ctuning/ck) format. Authors that go through the Artifact Evaluation process are also encouraged (but not mandated) to submit the supporting materials as “Source Materials” in the digital library. For details on how to submit supporting materials to the Artifact Evaluation process, please refer to: http://ctuning.org/ae/submission.html. For any additional question on the Artifact Evaluation process please contact the Artifact Evaluation Chair Flavio Vella. Important Dates Abstract submission: 7 September 2017 - EXTENDED - FIRM Position or full paper submission: 7 September 2017 - EXTENDED - FIRM Notification of acceptance: 3 October 2017 Camera-ready position and full papers: 10 October 2017 Workshop: 13 November 2017 Submissions Submission site: https://easychair.org/conferences/?conf=ia32017 All submissions should be in double-column, single-spaced letter format, with at least one-inch margins on each side and respect the ACM standard proceedings templates (sigconf) available at: https://www.acm.org/publications/proceedings-template. The proceedings of the workshop will be published in cooperation with ACM SIGHPC. Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four(4) pages for position papers including figures, tables and references. Organizers Antonino Tumeo, PNNL, US John Feo, PNNL/NIAC, US, Vito Giovanni Castellana, PNNL, US Artifact Evaluation Chair Flavio Vella, DIVIDITI, UK Publication Chair Marco Minutoli, PNNL, US Program Committee Scott Beamer, LBNL, US Michela Becchi, North Carolina State University, US Erik Boman, Sandia National Laboratories, US David Brooks, Harvard University, US Aydin Buluc, LBNL, US Sunita Chandrasekaran, University of Delaware, US Fabio Checconi, IBM, US Rajiv Gupta, Univerisity of California Riverside, US Maya Gokhale, LLNL, US Peter Kogge, Univ. of Notre Dame, US Vivek Kumar, Rice University, US John Leidel, Texas Tech University, US Kamesh Madduri, Pennsylvania State University, US Naoya Maruyama, RIKEN AICS, JP Tim Mattson, Intel, US Miquel Moreto, BSC and UPC, SP Richard Murphy, Micron Technology Inc, US Walid Najjar, University of California Riverside, US Maxim Naumov, NVIDIA, US Jacob Nelson, University of Washington, US Sreepathi Pai, University of Rochester, US Roger Pearce, LLNL, US Miquel Pericas, Chalmers University, SE Viktor Prasanna, University Of Southern California, US Alejandro Rico, ARM, US Jason Riedy, Georgia Institute of Technology, US Erik Saule, University of North Carolina at Charlotte, US John Shalf, LBNL, US Shaden Smith, University of Minnesota, US Bora Ucar, CNRS and LIP ENS Lyon, FR Ruud Van Der Pas, Oracle, US Flavio Vella, DIVIDITI, UK Ana Lucia Varbanescu, University of Amsterdam, NL

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