May 2018 - computational.science

CFP: YR-CONCUR 2018 - 8th Young Researchers Workshop on Concurrency Theory
by songfu＠shanghaitech.edu.cn 23 May '18

23 May '18

********************************************************************* YR-CONCUR 2018, Call for papers 8th Young Researchers Workshop on Concurrency Theory (YR-CONCUR), 2018 A satellite workshop of CONCUR 2018 September 3rd, 2018, Beijing, China (https://www.irif.fr/~cenea/yr-concur2018/) ********************************************************************* *Aims and objectives* This workshop aims at providing a platform for PhD students and young researchers who recently completed their doctoral studies, to exchange new results related to concurrency theory and receive feedback on their research. Focus is on informal discussions. Excellent master students working on concurrency theory are also encouraged to contribute. *Important Dates* Deadline for 4-page abstracts: June 8th, 2018 Notification of acceptance: July 6th, 2018 Workshop: September 3rd, 2018 *Format* YR-CONCUR 2018 is a satellite workshop of CONCUR 2018 and will be held on September 3rd, 2018. It is anticipated that many CONCUR participants will attend the YR-workshop (and vice versa). Presentations are selected on the basis of an abstract of up to 4 pages (incl. references) describing the research. No particular format is required. Submissions are judged on the expected interest in and quality of the talk. The accepted abstracts will be made available at the workshop, but no formal proceedings are planned. It is thus also allowed (and encouraged) to send results that have been published at other conferences (although preferably not at CONCUR 2018 or any of its other satellite workshops). *Submission* 4-page abstracts should be submitted via the YR-CONCUR 2018 submission page on the EasyChair system: https://easychair.org/conferences/?conf=yrconcur2018. *Organizers* Constantin Enea (IRIF, Université Paris Diderot (Paris 7), France) Fu Song (ShanghaiTech University, China) Dr. Fu SONG School of Information Science and Technology,ShanghaiTech University Addr: Room 1A-504C, SIST Building, No.393 Huaxia Middle Road, Pudong Area Shanghai Tel: +86-(0)21-20685397, +86-15921769918 Website:sist.shanghaitech.edu.cn/faculty/songfu

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Job Openings: Professor / Associate Professor / Assistant Professor (Computer Science) at Hong Kong Baptist University (PR380/17-18)
by comp hkbu 18 May '18

18 May '18

The Department of Computer Science <http://www.comp.hkbu.edu.hk/> of Hong Kong Baptist University <http://www.hkbu.edu.hk/> (HKBU), presently offers BSc, MSc, MPhil, and PhD programmes, now seeks outstanding applicants for the following faculty positions on substantiable-track. *Professor / Associate Professor / Assistant Professor (Computer Science) (PR380/17-18) * The appointees will teach, and are expected to manage programme at undergraduate and postgraduate levels, perform high-impact research, as well as contribute to professional and institutional services. Collaboration with other faculty members in research and teaching is also expected. Applicants should possess a PhD degree in Computer Science, Computer Engineering, Information Systems, or a related field, and sufficiently demonstrate abilities to conduct high-quality research in one of the Department's key research areas: (i) computational intelligence, (ii) databases and information management, (iii) networking and systems, and (iv) pattern recognition and machine learning. They will be encouraged to collaborate with colleagues within the Department to contribute to two special thematic applications including (a) health informatics and (b) secure and privacy-aware computing, and/or outside the Department to contribute to interdisciplinary research projects under our University's Research Cluster on Data Analytics and A.I. in X. Applicants should also demonstrate strong commitment to undergraduate and postgraduate teaching in computer science and/or information systems, possess track record of innovative research and high-impact publications, and demonstrate the ability to bid for and pursue externally-funded research programmes. Candidates for the senior positions should also have a strong track record of research and teaching accomplishments. Initial appointment will be made on a fixed-term contract of three years. Re-appointment thereafter is subject to mutual agreement and availability of funding. For enquiry, please contact Dr William Cheung, Head of Department (email: william [at] comp.hkbu.edu.hk). More information about the Department can be found at http://www.comp.hkbu.edu.hk. *Rank and salary will be commensurate with qualifications and experience.* *Application Procedure:* Applicants are invited to submit their applications at the HKBU e-Recruitment System (jobs.hkbu.edu.hk <https://jobs.hkbu.edu.hk/hrssers/persrequest?job_no=PR380/17-18>). Applicants should request two referees to send in confidential letters of reference, with PR number quoted on the letters, to the Personnel Office (Email: recruit [at] hkbu.edu.hk) direct. Applicants are requested to send in samples of publications, preferably three best ones out of their recent publications and recent teaching evaluation results. Applicants not invited for interview 4 months after the closing date may consider their applications unsuccessful. All application materials including publication samples, scholarly/creative works will not be returned after the completion of the recruitment exercise unless upon request. Details of the University's Personal Information Collection Statement can be found at http://pers.hkbu.edu.hk/pics. The University reserves the right not to make an appointment for the posts advertised, and the appointment will be made according to the terms and conditions then applicable at the time of offer. Review of applications will begin in *July 2018* and will continue until the position is filled. http://www.comp.hkbu.edu.hk/v1/?page=job_vacancies&id=450

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[CFP] IA^3 2018 - 8th Workshop on Irregular Applications: Architectures and Algorithms
by Tumeo, Antonino 17 May '18

17 May '18

[Apologies if you receive multiple copies of this CFP] IA^3 2018 8th Workshop on Irregular Applications: Architectures and Algorithms http://hpc.pnl.gov/IA3 In Conjuction with SC18 Sponsored by IEEE TCHPC -------------------- Call for Papers -------------------- Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers. Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years. This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to: - Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors - Network architectures and interconnect (including high-radix networks, optical interconnects) - Novel memory architectures and designs (including processors-in memory) - Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) - Modeling, simulation and evaluation of novel architectures with irregular workloads - Innovative algorithmic techniques - Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.) - Impact of irregularity on machine learning approaches - Parallelization techniques and data structures for irregular workloads - Data structures combining regular and irregular computations (e.g., attributed graphs) - Approaches for managing massive unstructured datasets (including streaming data) - Languages and programming models for irregular workloads - Library and runtime support for irregular workloads - Compiler and analysis techniques for irregular workloads - High performance data analytics applications, including graph databases Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation. -------------------- Important Dates -------------------- Abstract Submission: August 22, 2018 Position or Regular Paper Submission: August 29, 2018 Notification: September 28, 2018 Camera-ready: October 10, 2018 Workshop: November 12, 2018 Submissions Submission site: https://submissions.supercomputing.org Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers including figures, tables and references. Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix. The workshop proceedings will be published through IEEE TCHPC and will be included in the IEEE Xplore digital library. The templates are available at: http://www.ieee.org/conferences_events/conferences/publishing/templates.html. -------------------- Artifact Description & Evaluation -------------------- This edition of the workshop invites authors of regular papers to follow a reproducibility initiative like the main SC Conference, with specific appendices for the Artifact Description (AD) and the Artifact Evaluation (AE). Please refer to the SC reproducibility page for further details on the rationale behind AD and AE: https://sc18.supercomputing.org/submit/sc-reproducibility-initiative/. Authors of regular papers will be able to use up to one (1) additional page to provide an Artifact Description (AD) Appendix, describing the details of their software environments and computational experiments to the extent that an independent person could replicate their results. This additional page is voluntary, and must focus only on details on software environments and methods to execute the experiments. It should not add details on the proposed technical approaches. If a paper has no computational results, the appendix only needs to mention that computational results are not part of the paper. Additionally, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation (AE) process. The process is voluntary, but authors that will participate in the AE will be eligible for the Best Paper Award of the workshop. Supporting materials for the AE include access to the actual software artifact, shared pubblicly (for example, through the CK - Collective Knowledge - https://github.com/ctuning/ck format), and two (2) further additional pages of the paper that details how to reproduce the results of the paper. For details on how to submit supporting materials to the AE process, please refer to: http://ctuning.org/ae/submission.html. Authors participating in the AE will receive an assessment of the artifact, and the related badge on their paper. For any additional question on the AD and the AE please contact the Artifact Evaluation Chair Flavio Vella at flavio(a)dividiti.com<mailto:flavio@dividiti.com>. -------------------- Organizers -------------------- Antonino Tumeo (PNNL), antonino.tumeo(a)pnnl.gov<mailto:antonino.tumeo@pnnl.gov> John Feo (PNNL/NIAC), john.feo(a)pnnl.gov<mailto:john.feo@pnnl.gov> Vito Giovanni Castellana (PNNL), vitoGiovanni.castellana(a)pnnl.gov<mailto:vitoGiovanni.castellana@pnnl.gov> -------------------- Proceedings Chair -------------------- Marco Minutoli (PNNL and WSU), marco.minutoli(a)pnnl.gov<mailto:marco.minutoli@pnnl.gov> -------------------- Artifact Evaluation Chair -------------------- Favio Vella (DIVIDITI), flavio(a)dividiti.com<mailto:flavio@dividiti.com> -------------------- Technical Program Committee -------------------- Nesreen Ahmed, Intel, US Kubilay Atasu, IBM Zurich, CH Scott Beamer, LBNL, US Sanjukta Bhowmick, University of Nebraska Omaha, US Erik Boman, SNL, US David Brooks, Harvard University, US Aydin Buluc, LBNL, US Joe Eaton, NVIDIA, US Rajiv Gupta, UC Riverside, US Arif Khan, PNNL, US Farzad Khorasani, Georgia Tech, US Peter M. Kogge, University of Notre Dame, US Manoj Kumar, IBM TJ Watson, US John Leidel, Tactical Computing Labs, US Kamesh Madduri, Pennsylvania State University, US Naoya Maruyama, LLNL, US Miquel Moretó, Barçelona Supercomputing Center, ES Maxim Naumov, Facebook, US Fanny Nina-Paravecino, Northeastern University, US Sreepathi Pai, Rochester University, US Roger Pearce, LLNL, US Miquel Pericas, Chalmers University of Technology, SE Keshav Pingali, University of Texas at Austin, US Viktor K. Prasanna, University of Southern California, US Jason Riedy, Georgia Tech, US John Shalf, LBNL, US Shaden Smith, Intel, US Edgar Solomonik, University of Illinois at Urbana-Champaign, US Bora Uçar, French National Center for Scientific Research, FR Ruud van der Pas, Oracle, NL Ana Lucia Varbanescu, University of Amsterdam, NL Cheng Wang, Microsoft, US

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[New Book Release] Measuring Inconsistency in Information
by Vanina Martinez 16 May '18

16 May '18

============================================================ ======================================================= Apologies if you receive multiple copies of this message ============================================================ ========================================================= Measuring Inconsistency in Information John Grant and Maria Vanina Martinez (Eds) ============================================================ ========================================================= Published by College Publications URL: http://www.collegepublications.co.uk/logic/?00040 The concept of measuring inconsistency in information was developed by John Grant in a 1978 paper in the context of first-order logic. For more than 20 years very little was done in this area until in the early 2000s a number of AI researchers started to formulate new inconsistency measures primarily in the context of propositional logic knowledge bases. The aim of this volume is to survey what has been done so far, to expand inconsistency measurement to other formalisms, to connect it with related topics, and to provide ideas for further research in a topic that is particularly relevant now in view of the many inconsistencies in the massive amount of information available. The book contains 11 chapters. The first chapter, by John Grant, gives his original motivation for starting this field, explains why it was formulated in a highly mathematical manner, presents important material that was omitted from the original paper, and provides ideas about the use of dimensions in measuring inconsistency. The second chapter, by Matthias Thimm, is a survey that covers most of the research on inconsistency measures up to 2017. The other 9 chapters, all by experts either in inconsistency measures, or in the topic under consideration, or both, connect inconsistency measures with argumentation, disjunctive logic programming, fuzzy logic systems, modal logics, multiset representation, paraconsistent consequence, probabilistic logic, relational databases, and spatio-temporal databases. ============================================================ ========================================================= For more details, please go to: http://www.collegepublications.co.uk/logic/?00040 ============================================================ =========================================================

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Euro-EDUPAR Workshop 2018 - Deadline extended until May 27
by Rizos Sakellariou 15 May '18

15 May '18

Euro-EDUPAR Workshop 2018 - Deadline extended until May 27 August 27, 2018 Turin, Italy http://www.euroedupar.tu-darmstadt.de held in conjunction with Euro-Par 2018 https://europar2018.org Scope and objectives Parallel and Distributed Computing (PDC) is nowadays omnipresent. It is in all the computational environments, from mobile devices, laptops and desktops to clusters, large-scale data centers and supercomputers, often comprising CPUs and/or coprocessors of different types (GPU, MIC, FPGA). It becomes now vital to train new generations of scientists and engineers in the use of these computational systems: parallelism-related topics must be incorporated in Computer Science (CS) and Computer Engineering (CE) programs. In 2010 the IEEE Computer Society Technical Committee on Parallel Processing launched the Curriculum Initiative on Parallel and Distributed Computing, with Core Topics for Undergraduates, and in 2011 started the workshop EduPar, dedicated to Parallel and Distributed Computing Education. Given the differences in education in different parts of the world, the Euro-EDUPAR workshop aims to analyze PDC Education in a European context, taking into account the structure and organization of European education. In this context, the 4th European Workshop on Parallel and Distributed Computing Education for Undergraduate Students (Euro-EDUPAR) invites unpublished manuscripts from individuals or teams from academia, industry, and other educational and research institutes on topics pertaining to the teaching of PDC topics in the Computer Science and Engineering curriculum as well as in Computational Science with PDC and/or High Performance Computing (HPC) concepts, with emphasis on European undergraduate teaching. The workshop especially seeks papers that report on experiences incorporating PDC topics into undergraduate core courses taken by the majority of students on a degree course. Methods, pedagogical approaches, tools, and techniques that have potential for adoption across the European teaching community are of particular interest. Topics The topics of interest include, but are not limited to: 1. Parallel and Distributed Computing (PDC) teaching in the European space 2. Pedagogical issues in PDC, educational methods and learning mechanisms 3. Novel ways of teaching PDC topics, including informal learning environments 4. Curriculum design, models for incorporating PDC topics in core CS/CE curriculum 5. Experience with incorporating PDC topics into core CS/CE courses 6. Experience with incorporating PDC topics in the context of other applications learning 7. Pedagogical tools, programming environments, and languages for PDC 8. e-Learning, e-Laboratory, online courses related to PDC 9. PDC teaching experiences at non-university levels: secondary school, industry, etc Submission guidelines Submission The submissions will follow the Euro-Par guidelines, in PDF format, and should not exceed 12 pages in the Springer LNCS style, which can be downloaded from the Springer Web site. ftp://ftp.springernature.com/cs-proceeding/llncs/llncs2e.zip Paper submission is handled electronically (EasyChair). https://easychair.org/conferences/?conf=europar2018ws The 12-page limit is comprehensive (text, figures, references). Complete LaTeX sources must be provided for accepted papers. Short papers and work-in-progress papers can be submitted and presented at the workshop, but they will not be eligible for the post-conference proceedings published by Springer where only full papers between 10 and 12 pages long will be published. Submissions will be reviewed by at least 3 members of the Program Committee and will be assessed according to impact at European level, the novelty of contributions, impact on broader undergraduate curriculum, relevance to the goals of the workshop, results and methodology. The workshop proceedings will be published in a LNCS Euro-Par 2018 Workshops volume after the conference. Only full papers between 10 and 12 pages long which were presented at the workshop will be included. Important dates May 27, 2018: Paper submission deadline (extended) June 25, 2018: Author notification July 6, 2018: Paper due, for informal workshop proceedings August 27, 2018: Workshop (full day) October 2, 2018: Camera-ready paper (including LaTeX sources) deadline Travel support Authors of accepted papers may apply for travel support - typically granted in the form of a free registration. Organization General Co-Chairs Denis Trystram, Grenoble Institute of Technology, France Arnold L. Rosenberg, University of Massachusetts, USA Steering Committee Henri E. Bal, Vrije Universiteit, the Netherlands Alexey Lastovetsky, Univesity College Dublin, Ireland Christian Lengauer, University of Passau, Germany Pierre Manneback, University of Mons, Belgium Sushil K. Prasad, Georgia State University, USA Yves Robert, Ecole Normale Superieure de Lyon, France Arnold L. Rosenberg, University of Massachusetts, USA Rizos Sakellariou, University of Manchester, UK Cristina Silvano, Politecnico di Milano, Italy Paul G. Spirakis, University of Liverpool, UK Denis Trystram, Grenoble Institute of Technology, France Mateo Valero, Barcelona Supercomputing Center, Spain Vladimir Voevodin, Moscow State University, Russia Program Co-Chairs Felix Wolf, TU Darmstadt, Germany Rizos Sakellariou, University of Manchester, UK Program Committee Jorge G. Barbosa, University of Porto, Portugal Marian Bubak, AGH Krakow PL and University of Amsterdam, The Netherlands Aurelien Cavelan, University of Basel, Switzerland Sunita Chandrasekaran, University of Delaware, USA Gennaro Cordasco, Universita' della Campania "L. Vanvitelli", Italy Efstratios Gallopoulos, University of Patras, Greece Chryssis Georgiou, University of Cyprus, Cyprus Domingo Gimenez, University of Murcia, Spain Thilo Kielmann, Vrije Universiteit Amsterdam, The Netherlands Alexey Lastovetsky, University College Dublin, Ireland Vania Marangozova-Martin, Grenoble University, France Tomas Margalef, Universitat Autonoma de Barcelona, Spain Svetozar Margenov, Bulgarian Academy of Sciences, Bulgaria Lena Oden, Forschungszentrum J?lich, Germany Marcin Paprzycki, Polish Academy of Sciences, Poland Dana Petcu, West University of Timisoara, Romania Geppino Pucci, Universita' di Padova, Italy Erven Rohou, INRIA, France Emil Slusanschi, University Politehnica of Bucharest, Romania Juan Tourino, University of A Coru?a, Spain Jesper Larsson Tr?ff, Vienna University of Technology, Austria Vladimir Voevodin, Moscow State University, Russia Sponsorship This workshop is supported by SPPEXA, the DFG Program 1648 Software for Exascale Computing. Contact Felix Wolf <wolf(a)cs.tu-darmstadt.de>

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CALL FOR PAPERS SBAC-PAD 2018, International Symposium on Computer Architecture and High Performance Computing, Lyon, France, September 24-27, 2018
by Laurent Lefevre 14 May '18

14 May '18

CALL FOR PAPERS SBAC-PAD 2018 International Symposium on Computer Architecture and High Performance Computing Lyon, France September 24-27, 2018 http://avalon.ens-lyon.fr/sbac-pad SBAC-PAD is an international symposium, started in 1987, which has continuously presented an overview of new developments, applications, and trends in parallel and distributed computing technologies. SBAC-PAD is open for faculty members, researchers, specialists and graduate students around the world. In this edition, the symposium will be held at the École Normale Supérieure of Lyon, in France. Known as the Gastronomy Capital, Lyon is the 2nd largest economic and industrial region in France, and has become one of the favorite destinations for tourism in Europe. Lyon is also considered the most liveable city in France according to the Economist Intelligence Unit. Authors are invited to submit original manuscripts on a wide range of high-performance computing areas, including computer architecture, systems software, languages and compilers, algorithms, performance analysis, and applications. Topics of interest include (but are not limited to): - Application-specific systems - Architecture and programming support for emerging domains (Big Data, Deep Learning, Machine learning, Cognitive Systems) - Benchmarking, performance measurements, and analysis - Cloud, cluster, and edge/fog computing systems - Embedded and pervasive systems - GPUs, FPGAs and accelerator architectures - Languages, compilers, and tools for parallel and distributed programming - Modeling and simulation methodology - Operating systems and virtualization - Parallel and distributed systems, algorithms, and applications - Power and energy-efficient systems - Processor, cache, memory, storage, and network architecture - Real-world applications and case studies - Reconfigurable, resilient and fault-tolerant systems PAPER SUBMISSION Submissions must be in English, 8 pages maximum, following the IEEE conference formatting guidelines. To be published in the SBAC-PAD 2018 Conference Proceedings and to be eligible for publication at the IEEE Xplore (pending), one of the authors must register at the full rate. Authors may not use a single registration for multiple papers. Authors of selected papers will be invited to submit extended versions of their papers for publication on a selected journal. IMPORTANT DATES - Abstract deadline: May 25, 2018 - Paper deadline: June 1, 2018 - Rebuttal period: June 27-28, 2018 - Author notification: July 6, 2018 - Camera-ready: July 20, 2018 ORGANIZING COMMITTEE General Chairs - Laurent Lefèvre (Inria, ENS Lyon, University of Lyon, France) - Alfredo Goldman (Sao Paulo University, Brazil) - Marcos Dias de Assuncao (Inria, ENS Lyon, University of Lyon, France) Program Co-chairs - Rosa M Badia (Barcelona Supercomputing Center, Spain) - Manish Parashar (Rutgers University, USA) - Lucas Mello Schnorr (Federal University of Rio Grande do Sul, Brazil) PROGRAM COMMITTEE Computer Architecture Track Chair: Kalyana Chadalavada (Intel, USA) - Celso Mendes (University of Illinois at Urbana-Champaign, USA) - Cristiana Bentes (UERJ, Brazil) - Edson Borin (University of Campinas, Brazil) - Farah Fargo (University of Arizona, USA) - Felipe Maia Galvao Franca (COPPE-UFRJ, Brazil) - Jose Moreira (IBM, USA) - Kalyana Chadalavada (Intel, USA) - Naveen Cherukuri (NVIDIA, USA) - Rathish Jayabharathi (Intel, USA) - Rodolfo Azevedo (University of Campinas, Brazil) Networking and Distributed Systems Track Chair: Wagner Meira, Jr, (Federal University of Minas Gerais, Brazil) - Andrey Britto (UFCG, Brazil) - Bruno Schulze (LNCC, Brazil) - Carlos Varela (Rensselaer Polytechnic Institute, USA) - Domenico Talia (University of Calabria, Italy) - Dorgival Guedes Neto (UFMG, Brazil) - Elias P. Duarte Jr. (UFPR, Brazil) - Harold Castro (Universidad de los Andes, Colombia) - Javier Garcia-Blas (University Carlos III of Madrid, Spain) - Juan Durillo (University of Innsbruck, Austria) - Nicolae Bogdan (Huawei, China) - Omer Rana (Cardiff University, UK) - Priscila Solis (UnB, Brazil) - Rizos Sakellariou (University of Manchester, UK) - Rodrigo Fonseca (Brown, USA) - Ronaldo Ferreira (UFMS, Brazil) - Sandra Gesing (Notre Dame University, USA) - Zhiyi Huang (University of Otago, New Zealand) Parallel Applications and Algorithms Track Chair: Enrique Quintana-Ortí, (Universidad Jaime I, Spain) - Emmanuel Agullo (Inria, France) - José Ignacio Aliaga (Computer Science and Engineering Department, University Jaime I, Spain) - Hartwig Anzt (Karlsruhe Institute of Technology, Germany) - Michael Bader (Technical University of Munich, Germany) - Paolo Bientinesi (RWTH Aachen University, Germany) - Kei Davis (Los Alamos National Laboratory, USA) - Alba Melo (University of Brasilia, Brazil) - Pablo Ezzatti Udelar (Uruguay) - Mathieu Faverge (Bordeaux INP, France) - Domingo Gimenez (University of Murcia, Spain) - Daniel S. Katz (University of Illinois Urbana-Champaign, USA) - Hatem Ltaief (KAUST, Saudi Arabia) - Piotr Luszczek (University of Tennessee Knoxville, USA) - Viktor Prasanna (University of Southern California, USA) - Olaf Schenk (Universita della Svizzera Italiana, Switzerland) - Leonel Sousa (Lisbon University, Portugal) - Guillermo Taboada (University of A Coruña, Spain) - Pedro Valero-Lara (The University of Manchester, UK) - Jaroslaw Zola (State University of New York, USA) - Jairo Panetta (INPE, Brazil) Performance Evaluation Track Chair: Arnaud Legrand (CNRS/Inria/Université Grenoble Alpes, France) - Laura Carrington (San Diego Supercomputer Center/University of California, USA) - Cesar De Rose (PUCRS, Brazil) - Alfredo Goldman (University of São Paulo, Brazil) - Andreas Knupfer (TU Dresden, Germany) - Swann Perarnau (Argonne National Laboratory, USA) - Martin Schulz (Technical University of Munich, Germany) - Frederic Suter (CC IN2P3 / CNRS, France) System Software Track Chair: Adrien Lebre (IMT Atlantique/Inria/LS2N, France) - Rafael Asenjo (Dpt. Computer Architecture, Univ. Malaga. Spain) - Paolo Bellavista (University of Bologna, Italy) - Siegfried Benkner (University of Vienna, Austria) - Carlo Bertolli (IBM TJ Watson Research Center, United States) - Francisco Brasileiro (UFCG, Brazil) - Helene Coullon (Inria, France) - Michael Gerndt (Technical University of Munich, Germany) - Antonio J. Peña (Barcelona Supercomputing Center -BSC, Spain) - Mauricio Pillon (UDESC, Brazil) - Radu Prodan (University of Klagenfurt, Austria) - Mario Südholt (IMT Atlantique, France) - Cedric Tedeschi (Inria, France) - Ayal Zaks (Intel, Israel)

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CfP+CfA ::: IFIP World Computer Congress 2018
by Robert Wrembel 10 May '18

10 May '18

Call for Papers and Attendance INTERNATIONAL FEDERATION FOR INFORMATION PROCESSING WORLD COMPUTER CONGRESS Sep 17-21, 2018 Poznan, Poland wcc2018.org wcc2018.put.poznan.pl INTERNATIONAL FEDERATION FOR INFORMATION PROCESSING (IFIP) ------------------------------------------------------------------------ * The leading multinational organization in Information & Communications Technologies (ICT), established 60 years ago * Recognized by United Nations and other world bodies * Membership covers over 50 countries, with a total membership of over 350 000 * Includes over 100 Working Groups organized in 13 Technical Committees WORLD COMPUTER CONGRESS (WCC) ------------------------------------------------------------------------ The World Computer Congress is the main event of the International Federation For Information Processing, being organized since 1959. In the recent past, WCC was held in: Canada (2002), France (2004), Chile (2006), Italy (2008), Australia (2010), the Netherlands (2012), and Korea (2015). MAIN TOPICS OF WCC: http://wcc2018.org/program ------------------------------------------------------------------------ - Security and Privacy - Data Science - Big Data Management and Analysis - Enterprise Information Systems and Database Technologies - the Internet of Things - Entertainment Computing - Social Aspects of Information Technologies - the History of Computing CONTESTS ------------------------------------------------------------------------ - PhD Student Research Competition - Cybersecurity contest: Capture-the-Flag HIGHLIGHTS: http://wcc2018.put.poznan.pl/ ------------------------------------------------------------------------ Keynote talks ---------------- - Prof. Wil van der Aalst (one of the most cited computer scientists in the world, top expert in workflow management, process mining, Petri nets, business process management, process modeling, and process analysis) Talk title: Responsible Data Science in a Dynamic World - Dr. Jan Camenisch (a leading scientist in the area of privacy and cryptography, Principal Research Staff Member at IBM Research - Zurich) - Prof. Leslie Valiant (world-renowned for contributions to complexity theory, Turing Award holder) Talk title: What Needs to be Added to Machine Learning? - Shamika N. Sirimanne (world-renowned expert in disaster risk reduction) Available grants ---------------- - 7 participation grants for students presenting at PhD Student Research Competition (http://wcc2018.put.poznan.pl/PhD-Workshop) - 2-3 travel grants for PhD students from developing countries - 1 travel grant for a mature researcher from a developing country (http://wcc2018.put.poznan.pl/grants) CALL FOR PAPERS ------------------------------------------------------------------------ The following events have open calls for papers (for details see the web pages of individual events): http://wcc2018.put.poznan.pl/program - International Conference on Research and Practical Issues Enterprise Information Systems - IFIP Internet of Things Conference - International Symposium on Computer and Information Sciences - International Conference on Entertainment Computing - Histories of Computing in Eastern Europe - Semantics in Big Data Management - IT in Disaster Risk Reduction Conference - IT Research Workshop - Applied Data Science

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Ada-Europe 2018 - early registration until May 14
by Dirk Craeynest 08 May '18

08 May '18

----------------------------------------------------------------------- 2nd Call for Participation *** UPDATED Program Summary *** 23rd International Conference on Reliable Software Technologies - Ada-Europe 2018 18-22 June 2018, Lisbon, Portugal http://www.ada-europe.org/conference2018 Organized by Univ. Lisboa and Ada-Europe, in cooperation with ACM SIGAda, SIGBED, SIGPLAN and the Ada Resource Association (ARA) *** Early registration discount until May 14 *** *** Add tutorials to your conference registration *** http://www.ada-europe.org/conference2018/tutorials.html *** Use conference poster to promote event *** http://www.ada-europe.org/conference2018/posters/AE2018_poster.png ----------------------------------------------------------------------- The 23rd International Conference on Reliable Software Technologies - Ada-Europe 2018 will take place in Lisbon, Portugal, from June 18 to 22. As per its traditional style, the conference will span a full week, including, from Tuesday to Thursday, three days of scientific, technical and industrial programs, along with tutorials and workshops on Monday and Friday. The Ada-Europe series of conferences has over the years become a leading international forum for providers, practitioners and researchers in reliable software technologies. These events highlight the increased relevance of Ada in general and in safety- and security-critical systems in particular, and provide a unique opportunity for interaction and collaboration between academics and industrial practitioners. Extensive information is available on the conference web site, such as an overview of the program, the list of accepted papers and industrial presentations, and descriptions of workshops, tutorials, keynote presentations, and social events. Also check the conference web site for registration, accommodation and travel information, as well as promotional material such as a ready-to-print conference poster and the 16-page Advance Program brochure. Quick overview - Mon 18 & Fri 22: tutorials + workshops - Tue 19 - Thu 21: core program Proceedings - published by Springer - volume 10873 in Lecture Notes in Computer Science series - will be available at conference Program Chair - António Casimiro, LASIGE/U. Lisboa, Portugal casim at ciencias.ulisboa.pt Keynote speakers - Paulo Esteves-Veríssimo, University of Luxembourg, Luxembourg, "Security and Dependability Challenges of IT/OT Integration" - Carl Brandon, Vermont Technical College, USA, "From Physicist to Rocket Scientist, and how to make a CubeSat that works" - Erhard Plödereder, University of Stuttgart, Germany, "Vulnerabilities in Safety, Security, and Privacy" Workshops (full day) - "Runtime Verification and Monitoring Technologies for Embedded Systems" Workshop (RUME 2018) - 5th International Workshop on "Challenges and new Approaches for Dependable and Cyber-Physical Systems Engineering" (DeCPS 2018) Tutorials (full day) - "Recent Developments in SPARK 2014" Peter Chapin, Vermont Technical College, USA - "Scheduling analysis of AADL architecture models" Frank Singhoff, Lab-STICC/UBO, France Pierre Dissaux, Ellidiss Technologies, France Tutorials (half day) - "Access types and memory management in Ada 2012" Jean-Pierre Rosen, Adalog, France - "Design and architecture guidelines for trustworthy systems" William Bail, The MITRE Corporation, USA - "Numerics for the Non-Numerical Analyst" Jean-Pierre Rosen, Adalog, France - "Requirements development for safety and security critical systems" William Bail, The MITRE Corporation, USA - "Writing Contracts in Ada" Jacob Sparre Andersen, JSA Research & Innovation - "Introduction to Libadalang" R. Amiard, P.M. de Rodat Raphaël Amiard, Pierre-Marie de Rodat, AdaCore, France - "Unit-testing with Ahven" Jacob Sparre Andersen, JSA Research & Innovation - "Frama-C, a Framework for Analysing C Code" Julien Signoles, CEA LIST, France Papers and Presentations - 10 refereed technical papers and 4 presentations in sessions on Safety and Security, Ada 202X, Handling Implicit Overhead, Real-time Scheduling, New Application Domains - 12 industrial presentations and experience reports in sessions on Ada in Industry, Space Systems, V&V of Safety-Cricital Software, Software Methodologies - submissions by authors from 19 countries, and accepted contributions from Austria, France, Germany, Italy, Norway Poland, Portugal, South Korea, Spain, Sweden, Switzerland, UK, USA Vendor exhibition and networking area - area features exhibitor booths, project posters, reserved vendor tables, and general networking options - several companies already committed; others expected to confirm soon - vendor presentation sessions in core program Social events - each day: coffee breaks in the exhibition space and sit-down lunches offer ample time for interaction and networking - Tuesday evening: Ada-Europe General Assembly, followed by Welcome Reception on board of modern catamaran, to see Lisbon from a different perspective and watch the sunset from the Tagus river - Wednesday evening: transportation to restaurant "A Casa do Bacalhau", for the traditional Ada-Europe Conference Banquet; the name means "The House of the Codfish", so it is not too difficult to guess what is their speciality - Best Paper and Best Presentation awards will be handed out Registration - online registration is open at <http://www.ada-europe.org/conference2018/registration.html> - early registration discount up to Monday May 14, 2018 - additional discount for academia, Ada-Europe, ACM SIGAda, SIGBED and SIGPLAN members - student discounts are available - registration includes copy of printed proceedings at event - includes coffee breaks and lunches - three day conference registration includes all social events - tutorial fees reduced when taken together with 3-day conference - payment possible by credit card or bank transfer - see registration page for all details Promotion - recommended Twitter hashtags: #AdaEurope and/or #AdaEurope2018 - 16-page Advance Program brochure available online <http://www.ada-europe.org/conference2018/AdaEurope2018%20Advance%20Program.…> - support Ada-Europe 2018 with promotional poster available at <http://www.ada-europe.org/conference2018/posters/AE2018_poster.png> Please make sure you book accommodation as soon as possible. Lisbon will be very busy in that week. For more info and latest updates see the conference web site at <http://www.ada-europe.org/conference2018>. We look forward to seeing you in Lisbon in June 2018! ----------------------------------------------------------------------- Our apologies if you receive multiple copies of this announcement. Please circulate widely. Dirk Craeynest, Ada-Europe'2018 Publicity Chair Dirk.Craeynest(a)cs.kuleuven.be *** 23rd Intl.Conf.on Reliable Software Technologies - Ada-Europe'2018 *** June 18-22, 2018 ** Lisbon, Portugal *** http://www.ada-europe.org

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(CALL FOR PAPERS) PAW-ATM: Parallel Applications Workshop, Alternatives To MPI
by Morris, Karla NMN 08 May '18

08 May '18

************************************************ Call for Papers PAW-ATM: Parallel Applications Workshop, Alternatives To MPI Held in conjunction with SC 18, Dallas, TX <http://sourceryinstitute.github.io/PAW/> ************************************************ Summary As high-performance computing hardware incorporates increasing levels of heterogeneity, hierarchical organization, and complexity, parallel programming techniques necessarily grow in complexity or in their ability to abstract away complexity. The concurrent development of multi- and many-core processors, deep memory hierarchies, and accelerators and the variety of ways to combine these makes the low-level language route unmanageable for domain experts tasked with developing applications. The technologies that a competent developer might be expected to master and combine include MPI plus CUDA, OpenMP, and OpenACC, most commonly denoted MPI + X. This approach inherently saddles the developer with low-level details that might better be handled by high-level abstractions. Higher-level parallel programming models offer rich sets of abstractions that feel natural in the intended applications. Such languages and tools include (Fortran, UPC, Julia), systems for large-scale data processing and analytics (Spark, Tensorflow, Dask), and frameworks and libraries that extend existing languages (Charm++, Unified Parallel C++ (UPC++), Coarray C++, HPX, Legion, Global Arrays). While there are tremendous differences between these approaches, all strive to support better programmer abstractions for concerns such as data parallelism, task parallelism, dynamic load balancing, and data placement across the memory hierarchy. This workshop will bring together applications experts who will present concrete practical examples of using such alternatives to MPI in order to illustrate the benefits of high-level approaches to scalable programming. The workshop expands upon the two similar workshops, PAW16 and PAW17, by broadening the theme beyond partitioned global address space languages. We invite you to take part in the Parallel Applications Workshop, Alternatives To MPI, and to join this vibrant and diverse community of researchers and developers. Scope and Aims The scope of the PAW-ATM workshop is to provide a forum for exhibiting case studies of higher-level programming models as MPI alternatives in the context of applications as a means of better understanding applications of MPI alternatives. We encourage the submission of papers and talks detailing such applications, including characterizations of scalability and performance, of expressiveness and programmability, as well as any downsides or areas for improvement in existing higher-level programming models. In addition to informing other application programmers about the potential that is available through MPI alternatives, the workshop is designed to communicate these experiences to compiler vendors, library developers, and system architects in order to achieve broader support for high-level approaches to scalable programming. We also specifically encourage submissions covering big data analytics, deep learning, and other novel and emerging application areas, beyond well-established HPC domains. Topics include, but are not limited to: * Novel application development using parallel programming languages. * Examples that demonstrate performance, compiler optimization, error checking, and reduced software complexity. * Applications from big data analytics, bioinformatics, and other novel areas. * Performance evaluation of applications developed using MPI alternatives. * Algorithmic models enabled by high-level parallel abstractions. * Experience with the use of new compiler and runtime environments. * Libraries using or supporting MPI alternatives. * Benefits of hardware abstraction and data locality on algorithm implementation. Submissions Submissions are solicited in two categories: Full-length papers presenting novel research results: * Full-length papers will be published in the workshop proceedings in cooperation with IEEE TCHPC. Submitted papers must be original work that has not appeared in and is not under consideration for another conference or a journal. Papers shall not exceed eight (8) pages including text, appendices, references, and figures. Appendix pages related to the reproducibility initiative not included. Extended abstracts summarizing published/preliminary results: * Extended abstracts will be evaluated separately and will not be included in the published proceedings; they are intended for timely communications of novel work that is going to be formally submitted elsewhere at a later stage, and/or of already published work that is nonetheless deemed appropriate for dissemination in this venue. Extended abstracts shall not exceed four (4) pages. Accepted full-length papers will be given longer presentation slots at the workshop than the abstract-only option. Submissions shall be submitted through Linklings ( https://submissions.supercomputing.org ). Submissions must use 10pt fonts in the IEEE format ( https://www.ieee.org/conferences/publishing/templates.html ). The page limit includes figures, tables, and your appendices, but does not include references, for which there is no page limit. Reproducibility initiative dependencies (Artifact Description or Computational Results Analysis) are also not included in the page limit. PAW-ATM follows the reproducibility initiative of SC18, please refer to http://sourceryinstitute.github.io/PAW/ for additional information. WORKSHOP CHAIR * Karla Morris - Sandia National Laboratory ORGANIZING COMMITTEE * Bradford L. Chamberlain - Cray Inc. * Salvatore Filippone - Cranfield University * Costin Iancu - Lawrence Berkeley National Laboratory PROGRAM COMMITTEE CHAIR * Bill Long - Cray Inc. PROGRAM COMMITTEE * Bradford L. Chamberlain - Cray Inc. * Valentin Churavy - Massachusetts Institute of Technology * Salvatore Filippone - Cranfield University, UK * Alex Gittens - Rensselaer Polytechnic Institute * Costin Iancu - Lawrence Berkeley National Laboratory * Hartmut Kaiser - Louisiana State University * Laxmikant Kale - University of Illinois * Seung-Hwan Lim - Oak Ridge National Laboratory * Bill Long - Cray Inc. * Karla Morris - Sandia National Laboratories * Mitsuhisa Sato - RIKEN Advanced Institute for Computational Science * Sean Treichler - NVIDIA * Jeremiah J. Wilke - Sandia National Laboratories ADVISORY COMMITTEE * Damian W. I. Rouson - Sourcery Institute * Katherine A. Yelick - Lawrence Berkeley National Laboratory IMPORTANT DATES: * Submission Deadline: July 31, 2018 * Author Notification: September 1, 2018 * Camera Ready: October 1, 2018 * Workshop Date: November 11--16, 2018

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