August 2017 - computational.science

CFP: 3rd Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2017) at SC17: Extended abstracts due Sept. 1
by Jason D. Bakos 25 Aug '17

25 Aug '17

========================================================================== ** Call for Papers ** ========================================================================== Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2017) Held in conjunction with Supercomputing 2017 Friday Morning, November 17, 2017 Denver, CO http://h2rc.cse.sc.edu ========================================================================== Submission Deadline: September 1, 2017 (one page extended abstracts) ========================================================================== As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier to use high-level programming models for FPGAs. Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its third year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on legacy and new high-level programming models, optimizations specific to scientific computing and data analytics, tools for performance/energy improvements, FPGA computing in the cloud, and popular applications for reconfigurable computing such as machine learning and big data. ========================================================================== Submissions (one page extended abstract): Submissions are solicited that explore the state of the art in the use of FPGAs in heterogeneous high-performance computing architectures and, at a system level, in data centers and supercomputers. FPGAs may be considered from either or both the distributed, parallel and composable fabric of compute elements or from their dynamic reconfigurability. We particularly encourage submissions which focus on the mapping of algorithms and applications to heterogeneous FPGA-based systems as well as the overall impact of such architectures on the compute capacity, cost, power efficiency, and overall computational capabilities of data centers and supercomputers. Submissions may report on theoretical or applied research, implementation case studies, benchmarks, standards, or any other area that promises to make a significant contribution to our understanding of heterogeneous high-performance reconfigurable computing and will help to shape future research and implementations in this domain. A non-comprehensive list of potential topics of interest is given below: 1. FPGAs in Supercomputer, Cloud and Data Center: FPGAs in relation to challenges to Cloud/Data Center/Supercomputing posed by the end of Dennard scaling 2. Supercomputing, Cloud and Data Center Applications: Exploiting FPGA compute fabric to implement critical cloud/HPC applications 3. Leveraging Reconfigurability: Using reconfigurability for new approaches to algorithms used in cloud/HPC applications 4. Benchmarks: Compute performance and/or power and cost efficiency for cloud/HPC with heterogeneous architectures using FPGAs 5. Implementation Studies: Heterogenous Hardware and Management Infrastructure 6. Programming Languages/Runtimes/OS/Tools/Frameworks for Heterogeneous High Performance Reconfigurable Computing 7. Future-gazing: New Applications/The Cloud Enabled by Heterogeneous High Performance Reconfigurable Computing, Evolution of Computer Architecture in relation to Heterogeneous High Performance Reconfigurable Computing 8. Community building: Standards, consortium activity, open source, education, initiatives to enable and grow Heterogeneous High Performance Reconfigurable Computing Prospective authors are invited to submit original and unpublished contributions as a ONE PAGE EXTENDED ABSTRACT in ACM SIG Proceedings format. ========================================================================== You can submit your contribution(s) through a link on the H2RC website: http://h2rc.cse.sc.edu ========================================================================== Important dates: Submission Deadline: September 1, 2017 Acceptance Notification: October 15, 2017 Camera-ready Manuscripts Due: November 4, 2017 Workshop Date: November 17, 2017 ========================================================================== Workshop Format: H2RC is a half-day Friday workshop. It will be comprised of Keynote and invited talks and talks selected from paper submissions. ========================================================================== Organizing Committee: Workshop Organizers: Michaela Blott, Xilinx Franck Cappello, Argonne National Lab Torsten Hoefler, ETH Zurich Jason D. Bakos, University of South Carolina Program Committee: Rizwan Ashraf, Oak Ridge National Laboratory Paul Chow, University of Toronto Carl Ebeling, Altera Hans Eberle, NVIDIA Alan George, University of Florida Christoph Hagleitner, IBM Miriam Leeser, Northeastern University Viktor Prasanna, Univ. of Southern California Marco Santambrogio, Politecnico Di Milano Jeffrey Vetter, Oak Ridge National Lab -- Jason D. Bakos, Ph.D. Professor Dept. of Computer Science and Engineering Univ. of South Carolina 301 Main St., Suite 3A01L Columbia, SC 29208 803-777-8627 (voice), 803-777-3767 (fax) http://www.cse.sc.edu/~jbakos jbakos(a)cse.sc.edu

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[CFP] IA^3 2017 - Deadline Extended!
by Tumeo, Antonino 23 Aug '17

23 Aug '17

[Apologies if you receive multiple copies of this CFP] NEWS: DEADLINE EXTENDED TO SEPTEMBER 7! IA^3 2017 Seventh Workshop on Irregular Applications: Architectures and Algorithms http://hpc.pnl.gov/IA3/ November 13, 2017 In conjunction with SC17 In collaboration with ACM SIGHPC Sponsored by IEEE TCHPC Call for Papers Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, tables, sparse matrices, deep nets, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers. Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years. This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to: * Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors * Network architectures and interconnect (including high-radix networks, optical interconnects) * Novel memory architectures and designs (including processors-in memory) * Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) * Modeling, simulation and evaluation of novel architectures with irregular workloads * Innovative algorithmic techniques * Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.) * Impact of irregularity on machine learning approaches * Parallelization techniques and data structures for irregular workloads * Data structures combining regular and irregular computations (e.g., attributed graphs) * Approaches for managing massive unstructured datasets (including streaming data) * Languages and programming models for irregular workloads * Library and runtime support for irregular workloads * Compiler and analysis techniques for irregular workloads * High performance data analytics applications, including graph databases Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation. Artifact Evaluation For this edition of IA^3, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation process, similarly to the process followed for SC17. The participation to the Artifact Evaluation process is voluntary and will not change decisions regarding the paper. However, papers that undergo the evaluation process will receive a seal of approval on the paper, and will be able to participate in the BEST PAPER AWARD selection. DIVIDITI will provide an Amazon Gift Voucher (valued $200) to the authors of the paper that passes artifact evaluation with the highest score and that shares the artifact in the CK (Collective Knowledge - https://github.com/ctuning/ck) format. Authors that go through the Artifact Evaluation process are also encouraged (but not mandated) to submit the supporting materials as “Source Materials” in the digital library. For details on how to submit supporting materials to the Artifact Evaluation process, please refer to: http://ctuning.org/ae/submission.html. For any additional question on the Artifact Evaluation process please contact the Artifact Evaluation Chair Flavio Vella. Important Dates Abstract submission: 7 September 2017 - EXTENDED - FIRM Position or full paper submission: 7 September 2017 - EXTENDED - FIRM Notification of acceptance: 3 October 2017 Camera-ready position and full papers: 10 October 2017 Workshop: 13 November 2017 Submissions Submission site: https://easychair.org/conferences/?conf=ia32017 All submissions should be in double-column, single-spaced letter format, with at least one-inch margins on each side and respect the ACM standard proceedings templates (sigconf) available at: https://www.acm.org/publications/proceedings-template. The proceedings of the workshop will be published in cooperation with ACM SIGHPC. Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four(4) pages for position papers including figures, tables and references. Organizers Antonino Tumeo, PNNL, US John Feo, PNNL/NIAC, US, Vito Giovanni Castellana, PNNL, US Artifact Evaluation Chair Flavio Vella, DIVIDITI, UK Publication Chair Marco Minutoli, PNNL, US Program Committee Scott Beamer, LBNL, US Michela Becchi, North Carolina State University, US Erik Boman, Sandia National Laboratories, US David Brooks, Harvard University, US Aydin Buluc, LBNL, US Sunita Chandrasekaran, University of Delaware, US Fabio Checconi, IBM, US Rajiv Gupta, Univerisity of California Riverside, US Maya Gokhale, LLNL, US Peter Kogge, Univ. of Notre Dame, US Vivek Kumar, Rice University, US John Leidel, Texas Tech University, US Kamesh Madduri, Pennsylvania State University, US Naoya Maruyama, RIKEN AICS, JP Tim Mattson, Intel, US Miquel Moreto, BSC and UPC, SP Richard Murphy, Micron Technology Inc, US Walid Najjar, University of California Riverside, US Maxim Naumov, NVIDIA, US Jacob Nelson, University of Washington, US Sreepathi Pai, University of Rochester, US Roger Pearce, LLNL, US Miquel Pericas, Chalmers University, SE Viktor Prasanna, University Of Southern California, US Alejandro Rico, ARM, US Jason Riedy, Georgia Institute of Technology, US Erik Saule, University of North Carolina at Charlotte, US John Shalf, LBNL, US Shaden Smith, University of Minnesota, US Bora Ucar, CNRS and LIP ENS Lyon, FR Ruud Van Der Pas, Oracle, US Flavio Vella, DIVIDITI, UK Ana Lucia Varbanescu, University of Amsterdam, NL

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ESORICS 2017: Call for Participation
by Cristina Alcaraz 21 Aug '17

21 Aug '17

============================================================================== ESORICS 2017: CALL FOR PARTICIPATION 22nd European Symposium on Research in Computer Security Oslo, Norway — September 11-15, 2017 ============================================================================== WWW: https://www.ntnu.edu/web/esorics2017/ Overview ------------------------------------ ESORICS is the annual European research event in Computer Security. The Symposium started in 1990 and has been held in several European countries, attracting a wide international audience from both the academic and industrial communities. The 22nd European Symposium on Research in Computer Security (ESORICS 2017) will be held in Oslo, Norway. ESORICS 2017 spans a total of 3 days, featuring: * 3 keynote speeches (Cormac Herley, Paul Syverson, Sandro Etalle) * 54 paper presentations in 3 days (Sep 11-13) * 8 workshops (Sept 14 - 15) Presentations Program ------------------------------------ The 54 papers of ESORICS 2017 are distributed between **18 sessions** in **two parallel tracks**. Following is the list of paper presentations for the main ESORICS conference. For the workshop programs, please consult their corresponding websites: * SECPRE 2017: https://samosweb.aegean.gr/secpre2017/ * SecSE 2017: http://secse.org * CBT 2017: http://www.deic.uab.cat/~jherrera/CBT/ * DPM 2017: http://deic.uab.cat/conferences/dpm/dpm2017/ * STM 2017: http://stm2017.di.unimi.it * QASA 2017: http://www.iit.cnr.it/qasa2017/ * CyberICPS: http://www.ds.unipi.gr/cybericps2017/ * SIoT 2017: http://siot-workshop.org ### September 11 - Day 1 ########### 09:30 - 10:30 * Keynote: Cormac Herley - Justifying Security Measures - a Position Paper 11:00 - 12:30 * Session 1: Security of embedded things - Shortfall-based Optimal Placement of Security Resources for Mobile IoT Scenarios Antonino Rullo, Edoardo Serra, Elisa Bertino and Jorge Lobo - Analyzing the Capabilities of the CAN Attacker Sibylle Froeschle and Alexander Stühring - Boot Attestation: Secure Remote Reporting with Off-The-Shelf IoT Sensors Steffen Schulz, André Schaller, Florian Kohnhäuser, and Stefan Katzenbeisser * Session 2: Cryptographic Application I - Per-Session Security: Password-Based Cryptography Revisited Gregory Demay, Peter Gazi, Ueli Maurer and Björn Tackmann - Non-Interactive Provably Secure Attestations for Arbitrary RSA Prime Generation Algorithm Fabrice Benhamouda, Houda Ferradi, Rémi Géraud and David Naccache - Tightly Secure Ring-LWE Based Key Encapsulation with Short Ciphertexts Martin Albrecht, Emmanuela Orsini, Kenneth Paterson, Guy Peer and Nigel Smart 14:00 - 15:30 * Session 3: Documents and Authorship - Identifying Multiple Authors in a Binary Program Xiaozhu Meng, Barton Miller and Kwang-Sung Jun - Verifiable Document Redacting Herve Chabanne, Rodolphe Hugel and Julien Keuffer - Source Code Authorship Attribution using Long Short-Term Memory Based Networks Bander Alsulami, Edwin Dauber, Richard Harang, Spiros Mancoridis and Rachel Greenstadt * Session 4: Analysis of Security Protocols - Automated analysis of equivalence properties for security protocols using else branches Ivan Gazeau and Steve Kremer and Levente Buttyán - Secure Authentication in the Grid: A formal analysis of DNP3: SAv5 Cas Cremers, Martin Dehnel-Wild and Kevin Milner - Modular Verification of Protocol Equivalence in the Presence of Randomness Matthew Bauer, Rohit Chadha and Mahesh Viswanathan 16:00 - 17:30 * Session 5: Threat Analysis - Preventing Advanced Persistent Threats in Complex Control Networks Juan E. Rubio, Cristina Alcaraz and Javier Lopez - MTD CBITS: Moving Target Defense for Cloud-Based IT Systems Alexandru G. Bardas, Sathya C. Sundaramurthy, Xinming Ou and Scott A. Deloach - Is my attack tree correct? Maxime Audinot, Sophie Pinchinat and Barbara Kordy * Session 6: Side Channels and data leakage - On-Demand Time Blurring to Support Side-Channel Defense Weijie Liu, Debin Gao and Mike Reiter - Acoustic Data Exfiltration from Speakerless Air-Gapped Computers via Covert Hard-Drive Noise Mordechai Guri, Yosef Solewicz, Andrey Daidakulov and Yuval Elovici - Practical Keystroke Timing Attacks in Sandboxed JavaScript Moritz Lipp, Daniel Gruss, Michael Schwarz, David Bidner, Clémentine Maurice and Stefan Mangard ### September 12 - Day 2 ########### 09:00 - 10:00 * Keynote: Paul Syverson - The Once and Future Onion 10:30 - 12:00 * Session 7: Vulnerabilities and Malware - Mirage: Toward a Stealthier and Modular Malware Analysis Sandbox for Android Lorenzo Bordoni, Mauro Conti and Riccardo Spolaor - VuRLE: Automatic Vulnerability Detection and Repair by Learning from Examples Siqi Ma, Ferdian Thung, David Lo, Cong Sun and Robert Deng - Adversarial Examples for Malware Detection Kathrin Grosse, Nicolas Papernot, Praveen Manoharan, Backes Michael and Patrick McDaniel Russo * Session 8: Privacy in Systems - PerfWeb: How to Violate Web Privacy with Hardware Performance Events Berk Gulmezoglu, Andreas Zankl, Thomas Eisenbarth and Berk Sunar - SePCAR: A Secure and Privacy-enhancing Protocol for Car Access Provision Iraklis Symeonidis, Abdelrahaman Aly, Mustafa Asan Mustafa, Bart Mennink, Siemen Dhooghe and Bart Preneel - Privacy Implications of Room Climate Data Philipp Morgner, Christian Müller, Matthias Ring, Björn Eskofier, Christian Riess, Frederik Armknecht and Zinaida Benenson 13:30 - 15:00 * Session 9: Network security - Link-Layer Device Type Classification on Encrypted Wireless Traffic with COTS Radios Rajib Ranjan Maiti, Sandra Siby, Ragav Sridharan and Nils Ole Tippenhauer - Preventing DNS amplification attacks using the history of DNS queries with SDN Soyoung Kim, Sora Lee, Geumhwan Cho, Muhammad Ejaz Ahmed, Jaehoon Paul Jeong and Hyoungshick Kim - Zero Round-Trip Time for the Extended Access Control Protocol Jacqueline Brendel and Marc Fischlin * Session 10: Controlling Access - No sugar but all the taste! Memory Encryption without Architectural Support Panagiotis Papadopoulos, George Christou, Giorgos Vasiliadis, Evangelos Markatos and Sotiris Ioannidis - Tree-based Cryptographic Access Control James Alderman, Naomi Farley and Jason Crampton - Securing Data Analytics on SGX With Randomization Swarup Chandra, Vishal Karande, Zhiqiang Lin, Latifur Khan, Murat Kantarcioglu and Bhavani Thuraisingham 15:30 - 17:00 * Session 11: Information Flow - We are Family: Relating Information-Flow Trackers Musard Balliu, Daniel Schoepe and Andrei Sabelfeld - A Better Composition Operator for Quantitative Information Flow Analyses Kai Engelhardt - WebPol: Fine-grained Information Flow Policies for Web Browsers Abhishek Bichhawat, Vineet Rajani, Jinank Jain, Deepak Garg and Christian Hammer * Session 12: Blockchain and social networks - A Traceability Analysis of Monero’s Blockchain Amrit Kumar, Clément Fischer, Shruti Tople and Prateek Saxena -RingCT 2.0: A Compact Linkable Ring Signature Based Protocol for Blockchain Cryptocurrency Monero Shi-Feng Sun, Man Ho Au, Joseph Liu and Tsz Hon Yuen - Secure Computation in Online Social Networks Foteini Baldimtsi, Dimitrios Papadopoulos, Stavros Papadopoulos, Alessandra Scafuro and Nikos Triandopoulos ### September 13 - Day 3 ########### 09:00 - 10:00 * Keynote: Sandro Etalle - From Intrusion Detection to Software Design 10:30 - 12:30 * Session 13: Web Security - DeltaPhish: Detecting Phishing Webpages in Compromised Websites Igino Corona, Battista Biggio, Matteo Contini, Luca Piras, Roberto Corda, Mauro Mereu, Guido Mureddu, Davide Ariu and Fabio Roli - DOMPurify: Client-Side Protection against XSS and Markup Injection Mario Heiderich, Christopher Späth, and Jörg Schwenk - Quantifying Web Adblocker Privacy Arthur Gervais, Alexandros Filios, Vincent Lenders and Srdjan Capkun * Session 14: Cryptographic signatures - Reusing Nonces in Schnorr Signatures Marc Beunardeau, Aisling Connolly, Remi Geraud, David Naccache and Damien Vergnaud - How to Circumvent the Structure-Preserving Signatures Lower Bounds MEssam Ghadafi - Server-Supported RSA Signatures for Mobile Devices Ahto Buldas, Aivo Kalu, Peeter Laud and Mart Oruaas 13:30 - 15:00 * Session 15: Formal techniques - Inference-Proof Updating of a Weakened View under the Modification of Input Parameters Joachim Biskup and Marcel Preuß - Verifying Constant-Time Implementations by Abstract Interpretation Sandrine Blazy, David Pichardie and Alix Trieu - AVR Processors as a Platform for Language-Based Security Florian Dewald, Heiko Mantel and Alexandra Weber * Session 16: Privacy and garbled circuits - Labeled Homomorphic Encryption: Scalable and Privacy-Preserving Processing of Outsourced Data Manuel Barbosa, Dario Catalano and Dario Fiore - New Way for Privacy-Preserving Decision Tree Evaluation Raymond K. H. Tai, Jack P. K. Ma, Yongjun Zhao and Sherman S. M. Chow - Enforcing Input Correctness via Certification in Garbled Circuit Evaluation Yihua Zhang, Marina Blanton and Fattaneh Bayatbabolghani 15:30 - 17:00 * Session 17: Intrusion Detection - Secure IDS Offloading with Nested Virtualization and Deep VM Introspection Shohei Miyama and Kenichi Kourai - Network Intrusion Detection based on Semi-Supervised Variational Auto-Encoder Genki Osada, Kazumasa Omote and Takashi Nishide - LeaPS: Learning-Based Proactive Security Auditing for Clouds Suryadipta Majumdar, Yosr Jarraya, Momen Oqaily, Amir Alimohammadifar, Makan Pourzandi, Lingyu Wang and Mourad Debbabi * Session 18: Cryptographic Applications II - Multiple Rate Threshold FlipThem David Leslie, Chris Sherfield and Nigel Smart - Stringer: Measuring the Importance of Static Data Comparisons to Detect Backdoors and Undocumented Functionality Sam L. Thomas, Tom Chothia and Flavio D. Garcia - Generic Constructions for Fully Secure Revocable Attribute-Based Encryption Kotoko Yamada, Nuttapong Attrapadung, Keita Emura, Goichiro Hanaoka and Keisuke Tanaka

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[simu-conf] EXTENDED DEADLINE - WSC 2017 - Posters, Case Studies, PhD Colloquium, Vendor track
by vsim-conf＠sce.carleton.ca 18 Aug '17

18 Aug '17

Winter Simulation Conference (WSC) 2017 - Call for Papers December 3-6, 2017 Red Rock Casino Resort & Spa www.wintersim.org DEADLINE EXTENDED - SEPTEMBER 1 Posters, Case Studies, PhD Colloquium, Vendor tracks WSC TURNS 50: SIMULATION EVERYWHERE! With 360 accepted papers, panels, special tracks, and an amazing venue, this 50th Anniversary Winter Simulation Conference promises to be a very exciting event. This is a reminder that there are other upcoming deadlines: . Poster Track http://meetings2.informs.org/wordpress/wsc2017/poster-sessions/ . PhD Colloquium http://meetings2.informs.org/wordpress/wsc2017/phd-colloquium/ . Case Studies http://meetings2.informs.org/wordpress/wsc2017/tracks/#caseStudies . Vendor Track http://meetings2.informs.org/wordpress/wsc2017/tracks/#vendor KEYNOTE & TITAN SPEAKERS 50th Anniversary Keynote - Barry L Nelson Northwestern University WSC 2067: What Are The Chances? At the November 1967 "Conference on the Applications of Simulation Using GPSS" it seems unlikely that anyone was wondering if the conference would still be occupying a big hotel in 2017. Conferences persist for many reasons, but a technical conference like WSC has to remain relevant to users, vendors, researchers and consumers (not just hotels) to survive. If our kind of simulation vanished, then so (eventually) would WSC. What is required for simulation to "remain relevant" for the next 50 years? Without fear of having to answer for my crimes in 2067, I boldly speculate on what SHOULD matter for the next 10-20 years, if not the next 50, with a focus on our strength: dealing with uncertainty. 50th Anniversary Titans Robert G. Sargent Professor Emeritus - Syracuse University A Prospective on Fifty-Five Years of the Evolution of Scientific Respect for Simulation Bernard P. Zeigler Professor Emeritus of Electrical and Computer Engineering - University of Arizona MASM Keynote Stephane Dauzere-Peres Professor, Ecole des Mines de Saint-Etienne Achievements and Lessons Learned from a Long-term Academic-Industrial Collaboration Military Keynote Douglas Hodson Associate Professor, Professor of Computer Engineering at the Air Force Institute of Technology (AFIT) Military Simulation: A Ubiquitous Future 50th Anniversary Track Keynote Brian Hollocks Professor, Bournemouth University, Faculty of Management. History of Simulation in the United Kingdom Further information about submission and the conference: http://www.wintersim.org Twitter: @WSConf Facebook: https://www.facebook.com/wintersimulationconference/ [apologies for duplicated messages. Problems/issues: vsim-conf-owner(a)sce.carleton.ca]

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IEEE VP TA - Vote for Doug
by fzuconf 18 Aug '17

18 Aug '17

Dear Colleague, The 2017 IEEE elections are August 15 – October 2 and I am running for IEEE VP Technical Activities. My main goal is leveraging IEEE to strengthen members’ careers and “mobilize their future.” It would be my great honor to serve the IEEE community in this role, I hope for your support and your vote! Experience, vision and accomplishment count. My diverse background in industry – and my professional and technical contributions – uniquely qualify me to deal with our current and future challenges. If elected, I shall work with you to maintain and grow IEEE’s position as the world’s leading volunteer-driven professional association – one that focuses on growing careers. My platform includes expanding new technology initiatives, growing standards activities, building education and training, leveraging collaboration across IEEE and externally, achieving diversity, and perhaps most important, assuring affordability as we do more for members’ careers. My website, www.dougzuckerman.org, has more information about me and shares my thoughts on how we shall work together on the theme, "Mobilize Your Future!" Please vote for me, help spread the word, and encourage your friends and colleagues to do likewise. Thanks, Doug Dr. Douglas N. Zuckerman IEEE Life Fellow IEEE Board of Directors – Division III Director (2012-13) IEEE Communications Society President (2008-9) IEEE Technical Activities Board Member (2008-9, 2012-13) IEEE Future Directions Committee (2014 - current) Senior Scientist, Telcordia Technologies (Retired) Consultant, Vencore Labs (www.vencorelabs.com) Ocean, New Jersey, USA Vote August 15th – October 2nd at www.ieee.org/elections. -- | | | Dr. Douglas N. Zuckerman | Candidate for IEEE VP Technical Activities | Ocean, New Jersey, USA | Campaign Website | | | ftin | |

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CFP: 3rd Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2017) at SC17: Extended abstracts due Sept. 1
by Jason D. Bakos 18 Aug '17

18 Aug '17

========================================================================== ** Call for Papers ** ========================================================================== Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2017) Held in conjunction with Supercomputing 2017 Friday Morning, November 17, 2017 Denver, CO http://h2rc.cse.sc.edu ========================================================================== Submission Deadline: September 1, 2017 (one page extended abstracts) ========================================================================== As conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier to use high-level programming models for FPGAs. Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its third year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on legacy and new high-level programming models, optimizations specific to scientific computing and data analytics, tools for performance/energy improvements, FPGA computing in the cloud, and popular applications for reconfigurable computing such as machine learning and big data. ========================================================================== Submissions (one page extended abstract): Submissions are solicited that explore the state of the art in the use of FPGAs in heterogeneous high-performance computing architectures and, at a system level, in data centers and supercomputers. FPGAs may be considered from either or both the distributed, parallel and composable fabric of compute elements or from their dynamic reconfigurability. We particularly encourage submissions which focus on the mapping of algorithms and applications to heterogeneous FPGA-based systems as well as the overall impact of such architectures on the compute capacity, cost, power efficiency, and overall computational capabilities of data centers and supercomputers. Submissions may report on theoretical or applied research, implementation case studies, benchmarks, standards, or any other area that promises to make a significant contribution to our understanding of heterogeneous high-performance reconfigurable computing and will help to shape future research and implementations in this domain. A non-comprehensive list of potential topics of interest is given below: 1. FPGAs in Supercomputer, Cloud and Data Center: FPGAs in relation to challenges to Cloud/Data Center/Supercomputing posed by the end of Dennard scaling 2. Supercomputing, Cloud and Data Center Applications: Exploiting FPGA compute fabric to implement critical cloud/HPC applications 3. Leveraging Reconfigurability: Using reconfigurability for new approaches to algorithms used in cloud/HPC applications 4. Benchmarks: Compute performance and/or power and cost efficiency for cloud/HPC with heterogeneous architectures using FPGAs 5. Implementation Studies: Heterogenous Hardware and Management Infrastructure 6. Programming Languages/Runtimes/OS/Tools/Frameworks for Heterogeneous High Performance Reconfigurable Computing 7. Future-gazing: New Applications/The Cloud Enabled by Heterogeneous High Performance Reconfigurable Computing, Evolution of Computer Architecture in relation to Heterogeneous High Performance Reconfigurable Computing 8. Community building: Standards, consortium activity, open source, education, initiatives to enable and grow Heterogeneous High Performance Reconfigurable Computing Prospective authors are invited to submit original and unpublished contributions as a ONE PAGE EXTENDED ABSTRACT in ACM SIG Proceedings format. ========================================================================== You can submit your contribution(s) through a link on the H2RC website: http://h2rc.cse.sc.edu ========================================================================== Important dates: Submission Deadline: September 1, 2017 Acceptance Notification: October 15, 2017 Camera-ready Manuscripts Due: November 4, 2017 Workshop Date: November 17, 2017 ========================================================================== Workshop Format: H2RC is a half-day Friday workshop. It will be comprised of Keynote and invited talks and talks selected from paper submissions. ========================================================================== Organizing Committee: Workshop Organizers: Michaela Blott, Xilinx Franck Cappello, Argonne National Lab Torsten Hoefler, ETH Zurich Jason D. Bakos, University of South Carolina Program Committee: Rizwan Ashraf, Oak Ridge National Laboratory Paul Chow, University of Toronto Carl Ebeling, Altera Hans Eberle, NVIDIA Alan George, University of Florida Christoph Hagleitner, IBM Miriam Leeser, Northeastern University Viktor Prasanna, Univ. of Southern California Marco Santambrogio, Politecnico Di Milano Jeffrey Vetter, Oak Ridge National Lab -- Jason D. Bakos, Ph.D. Professor Dept. of Computer Science and Engineering Univ. of South Carolina 301 Main St., Suite 3A01L Columbia, SC 29208 803-777-8627 (voice), 803-777-3767 (fax) http://www.cse.sc.edu/~jbakos jbakos(a)cse.sc.edu

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WHPC Workshop @ SC17 - Poster Deadline Extended
by Toni Collis 17 Aug '17

17 Aug '17

================================================================= 7th International Women in HPC workshop Sunday November 12th 2017 — Denver, CO, USA Call for posters and participation - deadline for posters extended: 27th August 2017 https://www.womeninhpc.org/whpc-sc17/workshop/ <https://www.womeninhpc.org/whpc-sc17/workshop/> ================================================================= Call for posters: Deadline extended Deadline for submissions: August 27th 2017 AOE Women in HPC will once again attend the Supercomputing conference to discuss diversity and inclusivity topics. Activities will bring together women from across the international HPC community, provide opportunities to network, showcase the work of inspiring women, and discuss how we can all work towards improving the under-representation of women in supercomputing. The 7th International Women in High Performance Computing (WHPC) workshop at SC17 in Denver brings together the HPC community to discuss the growing importance of increasing diversity in the workplace. This workshop will recognize and discuss the challenges of improving the proportion of women in the HPC community, and is relevant for employers and employees throughout the supercomputing workforce who are interested in addressing diversity. Sessions include: - Improving Diversity in the Workplace: What methods have been put in place and tested to improve workplace diversity and inclusion? - Career Development and Mentoring: Skills to thrive; sharing your experiences and advice on how to succeed in the workplace. - Virtual Poster Showcase: Highlighting work from women across industry and academia. Call for posters: Deadline extended Deadline for submissions: August 27th 2017 AOE As part of the workshop, we invite submissions from women in industry and academia to present their work as a virtual poster. This will promote the engagement of women in HPC research and applications, provide opportunities for peer to peer networking, and the opportunity to interact with female role models and employers. Submissions are invited on all topics relating to HPC from users and developers. All abstracts should emphasise the computational aspects of the work, such as the facilities used, the challenges that HPC can help address and any remaining challenges etc. For full details please see: http://www.womeninhpc.org/whpc-sc17/workshop/submit/ <http://www.womeninhpc.org/whpc-sc17/workshop/submit/> Workshop Committee Chairs - Workshop Chair: Toni Collis, EPCC, UK and Women in HPC Network, UK - Poster Chair: Misbah Mubarak, Argonne National Laboratory, USA - Mentoring Chair: Elsa Gonsiorowski, Lawrence Livermore National Laboratory, USA - Publicity Chair: Kimberly McMahon, McMahon Consulting, USA Steering and Organisation Committee - Sunita Chandrasekaran, University of Delaware, USA - Trish Damkroger, Intel, USA - Kelly Gaither, TACC, USA - Rebecca Hartman-Baker, NERSC, USA - Daniel Holmes, EPCC, UK - Adrian Jackson, EPCC, UK - Alison Kennedy, Hartree Centre, STFC, UK - Lorna Rivera, CEISMC, Georgia Institute of Technology, USA Programme Committee (for early career posters) - Sunita Chandrasekaran, University of Delaware, USA - Toni Collis, EPCC, UK and Women in HPC Network, UK - Elsa Gonsiorowski, Lawrence Livermore National Laboratory, USA - Rebecca Hartman-Baker, NERSC, USA - Daniel Holmes, EPCC, UK - Adrian Jackson, EPCC, UK - Alison Kennedy, Hartree Centre, STFC, UK - Misbah Mubarak, Argonne National Laboratory, USA - Lorna Rivera, CEISMC, Georgia Institute of Technology, USA - Jesmin Jahan Tithi, Parallel Computing Lab, Intel Corporation, USA The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336.

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Call For Papers [Updated Information]: ESPM2@SC17 - Third International Workshop on Extreme Scale Programming Models and Middleware
by Hari Subramoni 15 Aug '17

15 Aug '17

======================================================================== Call For Papers Third International IEEE Workshop on Extreme Scale Programming Models and Middleware (ESPM2 2017) November 12, 2017, Denver, Colorado to be held in conjunction with SuperComputing 2017, November 12 - 16, 2017 Denver, Colorado http://nowlab.cse.ohio-state.edu/espm2/ ======================================================================== Next generation architectures and systems being deployed are characterized by high concurrency, low memory per-core, and multiple levels of hierarchy and heterogeneity. These characteristics bring out new challenges in energy efficiency, fault-tolerance and, scalability. It is commonly believed that software has the biggest share of the responsibility to tackle these challenges. In other words, this responsibility is delegated to the next generation programming models and their associated middleware/runtimes. This workshop focuses on different aspects of programming models such as task-based parallelism (Charm++, OCR, Habanero, Legion, X10, HPX, etc), PGAS (OpenSHMEM, UPC, CAF, Chapel, UPC++, etc.), BigData (Hadoop, Spark, etc), Deep Learning (Caffe, Microsoft CNTK, Google TensorFlow), directive-based languages (OpenMP, OpenACC) and Hybrid MPI+X, etc. It also focuses on their associated middleware (unified runtimes, interoperability for hybrid programming, tight integration of MPI+X, and support for accelerators) for next generation systems and architectures. The ultimate objective of the ESPM2 workshop is to serve as a forum that brings together researchers from academia and industry working in the areas of programming models, runtime systems, compilers, programming languages, and application developers. ESPM2 2017 will be held as a full day workshop in conjunction with the SuperComputing (SC 2017), Denver, Colorado, USA, Sunday, November 12th, 2017. Topics ------ ESPM2 2017 welcomes original submissions in a range of areas, including but not limited to: * New programming models, languages and constructs for exploiting high concurrency and heterogeneity * Experience with and improvements for existing parallel languages and run-time environments such as: - MPI - PGAS (OpenSHMEM, UPC, CAF, Chapel, UPC++, etc.) - Directive-based programming (OpenMP, OpenACC) - Asynchronous Task-based models (Charm++, OCR, Habanero, Legion, X10, HPX, etc) - Hybrid MPI+X models - BigData (Hadoop, Spark, etc), and - Deep Learning (Caffe, Microsoft CNTK, Google TensorFlow) * Parallel compilers, programming tools, and environments * Software and system support for extreme scalability including fault tolerance * Programming environments for heterogeneous multi-core systems and accelerators such as KNL, OpenPOWER, ARM, GPUs, FPGAs, MICs, and DSPs Papers should present original research and should provide sufficient background material to make them accessible to the broader community. Best Paper Award ---------------- Intel has generously offered to sponsor the Best Paper Award. This award will be given to the author(s) of the paper selected by the Technical Program Committee and the Program Chairs. The award will be determined from viewpoints of the technical and scientific merits, impact on the science and engineering of the research work and the clarity of presentation of the research contents in the paper. Keynote Speakers ---------------- We are happy to announce that Prof. William D. Gropp, Interim Director and Chief Scientist at the National Center for Supercomputing Applications and the Thomas M. Siebel Chair in Computer Science at the University of Illinois Urbana-Champaign will deliver the keynote address at ESPM2'17. Panel Information ----------------- Panel Topic : Effective Programming Models for Deep Learning at Scale Panel Moderator : Daniel Holmes, EPCC, The University of Edinburgh, UK. Panel Members : Coming soon! Paper Submission and Registration --------------------------------- Abstracts and papers need to be submitted via the EasyChair conference system. EasyChair URL for ESPM2'17: https://easychair.org/conferences/?conf=espm22017 Submissions should not exceed 8 pages using ACM format with 10pt font. Each submission must be a single PDF file. Papers must be submitted in PDF format (readable by Adobe Acrobat Reader 5.0 and higher) and formatted for 8.5" x 11" (U.S. Letter). The manuscript should be formatted according to ACM format (see http://www.acm.org/sigs/publications/proceedings-templates) Papers should present original research and should provide sufficient background material to make them accessible to the broader community. It should not be submitted in parallel to any other conference or journal. At least one of the authors of each accepted paper must register as a participant of the workshop and present the paper at the workshop, in order to have the paper published in the proceedings. Each research paper will be taken through a comprehensive peer review process by an internationally recognized group of experts in the field. Papers will be evaluated along the metrics of a) Quality of Presentation; b) Novelty / Originality; c) Relation to State of the Art; d) Technical Strength; e) Significance of Work; and f) Relevance to Workshop. Every effort will be made to ensure that each paper receives multiple reviews. Please contact the Program Chairs for any questions/clarifications Proceedings Information ----------------------- ACM SigHPC will publish the workshop proceedings which will be available through the ACM Digital Library. The camera-ready versions need to be submitted via the EasyChair conference management system. The link to the submission site will be provided soon. Please contact the Program Chairs for any questions/clarifications. Important Dates --------------- Technical paper submission deadline : 11:59 PM, AoE, August 31, 2017 Author notification : October 1, 2017 Camera-ready deadline : 11:59 PM, AoE, October 7, 2017 Workshop : Sunday, November 12, 2017 ESPM2'17 Workshop Organizers ------------------------------ Hari Subramoni, The Ohio State University Karl Schulz, Intel Corporation Dhabaleswar K. (DK) Panda, The Ohio State University Program Committee ----------------- * Guang R. Gao, University of Delaware * Vladimir Getov, University of Westminster, UK * Jeff Hammond, Intel Labs * Michael A. Heroux, Sandia National Laboratories * Costin Iancu, Lawrence Berkeley National Laboratory * Darren Kerbyson, Pacific Northwest National Laboratory * Guangming Tan, Institute of Computing Technology, Chinese Academy of Sciences, China * Olivier Tardieu, IBM T.J. Watson Research Center * Daniel Tian, The Portland Group * Sean Treichler, NVIDIA Corporation * Abhinav Vishnu, Pacific Northwest National Laboratory Further Information ------------------- See the ESPM2'17 website at http://nowlab.cse.ohio-state.edu/espm2/ Thanks, The ESPM2'17 Organizing Committee.

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[Deadline Extended] - BI 2017 - Call for Abstracts
by Yang 15 Aug '17

15 Aug '17

[Apologies if you receive this more than once] CALL FOR ABSTRACTS The 2017 International Conference on Brain Informatics (BI'17) "Investigating the Brain and Mind from Informatics Perspective" November 16-18, 2017, Beijing, China Homepage: http://bii.ia.ac.cn/bi-2017/ --------------------------------------- SUBMISSION DEADLINE: August 30, 2017 One-line submission: https://wi-lab.com/cyberchair/2017/bi17/scripts/submit.php?subarea=B --------------------------------------- *** INVITED SPEECHES *** 1. "Multimodal Modelling of Network Propagation of Neuropathology in Dementia" Alan Evans (McGill University, Canada) 2. "Neural Correlates of Word, Sentence and Story Comprehension" Tom Mitchell (Carnegie Mellon University, US) 3. "The Cognitive Neural Basis of Object Knowledge" Yanchao Bi (Beijing Normal University, China) 4. "Harnessing Large-Scale Data-Sharing to Drive Discovery and Bench-to-Bedside Translation in Traumatic Brain Injury and Spinal Cord Injury" Adam Ferguson (University of California San Francisco, US) 5. "Computational Psychophysiology Based Research Methodology for Mental Health" Bin Hu (Lanzhou University, China) 6. "Multiscale Gene Expression Signatures in the Mammalian Brain in Health and Disease" Michael Hawrylycz (Allen Institute for Brain Science, US) 7. "Machine Learning in Medical Imaging Analysis" Dinggang Shen (University of North Carolina at Chapel Hill, US) *** WORKSHOPS AND SPECIAL SESSIONS *** ++++++++++++++++++++++++++++++++++++++++++++ Abstract submission (TYPE II) is still open! ++++++++++++++++++++++++++++++++++++++++++++ To submit abstracts to workshops/special sessions, please visit http://bii.ia.ac.cn/bi-2017/workshops.htm # Workshop on Brain and Artificial Intelligence (BAI 2017) Organizers: Yi Zeng, Chinese Academy of Sciences, China Shuliang Wang, Beijing Institute of Technology, China # Workshop on Knowledge Representation: Brain and Machine (KRBM 2017) Organizers: Yanchao Bi, Beijing Normal University, China Yi Zeng, Chinese Academy of Sciences, China # Workshop on Affective, Psychological and Physiological Computing (APPC 2017) Organizers: Bin Hu, Lanzhou University, China Zhijun Yao, Lanzhou University, China Mi Li, Beijing University of Technology, China # Workshop on Big Data and Visualization for Brainsmatics (BDVB 2017) Organizers: Qingming Luo, Huazhong University of Science and Technology, China Anan LI, Huazhong University of Science and Technology, China # Workshop on Brain Big Data Based Wisdom Service (BBDBWS 2017) Organizer: Jiajin Huang, Beijing University of Technology, China # Workshop on Semantic Technology for eHealth (STeH 2017) Organizers: Jiao Li, Chinese Academy of Medical Sciences, China Zhisheng Huang, Vrije University Amsterdam, The Netherlands # Workshop on Big Data Neuroimaging Analytics for Brain and Mental Health (BDNABMH 2017) Organizer: Shouyi Wang, University of Texas at Arlington, USA # Workshop on Novel Methods of the Brain Imaging in the Clinical and Preclinical Neuroscience (NMBICPN 2017) Organizers: Vassiliy Tsytsarev, University of Maryland School of Medicine, USA Vicky Yamamoto, Keck School of Medicine of USC, USA Yan Li, University of Southern Queensland, Australia # The 1st International Workshop on Deep Learning in Brain MRI and Pathology Images (DLBMPI 2017) Organizers: Yan Xu, School of Biological Science and Medical Engineering, BUAA Eric Chang, Microsoft Research Asia # Workshop on Mesoscopic Brainformatics (MBAI 2017) Organizers: Dezhong Yao, University of Electronic Science and Technology of China, China Pedro A. Valdes-Sosa, University of Electronic Science and Technology of China, China Yong He, Beijing Normal University, China Li Dong, University of Electronic Science and Technology of China, China # Special Session on Brain Informatics in Neurogenetics (BIN 2017) Organizers: Hong Liang, Harbin Engineering University, China Lei Du, Northwestern Polytechnical University, China Li Shen, Indiana University School of Medicine, USA # Special Session on BigNeuron Project (BP 2017) Organizers: Zhi Zhou, Allen Institute for Brain Sciences, USA Min Liu, Hunan University, China ================================================== Brain Informatics (BI) conference series provides a premier forum to bring together researchers and practitioners in the fields of neuroscience, cognitive science, computer science, data science, artificial intelligence, information communication technologies, and neuroimaging technologies. BI'17 addresses the computational, cognitive, physiological, biological, physical, ecological and social perspectives of brain informatics, as well as topics relating to mental health and well-being. It also welcomes emerging information technologies, including but not limited to Internet/Web of Things (IoT/WoT), cloud computing, big data analytics and interactive knowledge discovery related to brain research. BI'17 also encourages submissions that explore how advanced computing technologies are applied to and make a difference in various large-scale brain studies and their applications. BI'17 welcomes paper submissions (full paper and abstract submissions). Both research and application papers are solicited. All submitted papers will be reviewed on the basis of technical quality, relevance, significance and clarity. Accepted full papers will be included in the proceedings by Springer LNCS/LNAI. Workshop, Special-Session and Tutorial proposals, and Industry/Demo-Track papers are also welcome. The organizers of Workshops and Special-Sessions are invited to prepare a book proposal based on the topics of the workshop/special session for possible book publication in the Springer-Nature Brain Informatics & Health book series (http://www.springer.com/series/15148) *** Topics and Areas *** Track 1: Cognitive and Computational Foundations of Brain Science Track 2: Investigations of Human Information Processing Systems Track 3: Brain Big Data Analytics, Curation and Management Track 4: Informatics Paradigms for Brain and Mental Health Track 5: Brain-Inspired Intelligence and Computing IMPORTANT DATES : =========================== May 1, 2017: Submission deadline for full papers June 20, 2017: Notification of full paper acceptance July 20, 2017: Submission deadline for workshop/special-session papers August 30, 2017: Submission deadline for abstracts (TYPE-II) (for both main conference and workshops/special sessions) November 16, 2017: Tutorials, workshops and special-sessions November 17-18, 2017: Main conference ABSTRACT (TYPE-II) SUBMISSIONS : ================================= (Submission Deadline: August 30, 2017): Abstracts have a word limit of 500 words. Experimental research is particularly welcome. Accepted abstract submissions will be included in the conference program, and will be published as a single, collective proceedings volume. Title: Include in the title of the abstract all words critical for a subject index. Write your title in sentence case (first letter is capitalized; remaining letters are lower case). Do not bold or italicize your full title. Author: List all authors who contributed to the work discussed in the abstract. The presenting author must be listed in the first author slot of the list. Be prepared to submit contact information as well as conflict of interest information for each author listed. Abstract: Enter the body of the abstract and attach any applicable graphic files or tables here. Do not re-enter the title, author, support, or other information that is collected in other steps of the submission form. Presentation Preference: Authors may select from three presentation formats when submitting an abstract: "poster only", "talk preferred" or "no preference." The "talk preferred" selection indicates that you would like to give a talk, but will accept a poster format if necessary. Marking "poster only" indicates that you would not like to be considered for an oral-presentation session. Selecting "no preference" indicates the author's willingness to be placed in the best format for the program. Each paper or abstract requires one sponsoring attendee (i.e. someone who registered and is attending the conference). A single attendee can not sponsor more than two abstracts or papers. Oral presentations will be selected from both full length papers and abstracts. ----------------------------------------------- One-line submission: https://wi-lab.com/cyberchair/2017/bi17/scripts/submit.php?subarea=B ----------------------------------------------- *** Post-Conference Journal Publication *** The Brain Informatics conferences have the formal ties with Brain Informatics journal (Springer-Nature, http://www.springer.com/40708) Accepted abstracts from the conference will be expanded and revised for possible inclusion in the Brain Informatics journal each year. It is fully sponsored and no any article-processing fee charged for authors of Brain Informatics conference. ORGANIZERS ========== General Chairs Bo Xu (Chinese Academy of Sciences, China) Hanchuan Peng (Allen Institute for Brain Sciences, USA) Qingming Luo (Huazhong University of Science and Technology, China) Program Committee Chairs Yi Zeng (Chinese Academy of Sciences, China) Yong He (Beijing Normal University, China) Jeanette Kotaleski (Karolinska Institute, Sweden) Maryann Martone (University of California, San Diego, USA) Organizing Chairs Ning Zhong (Maebashi Institute of Technology, Japan, and Beijing Advanced Innovation Center for Future Internet Technology, Beijing University of Technology, China Jianzhou Yan (Beijing Advanced Innovation Center for Future Internet Technology, Beijing University of Technology, China) Shengfu Lu (Beijing Advanced Innovation Center for Future Internet Technology, Beijing University of Technology, China) Workshop/Special-Session Chairs An'an Li (Huazhong University of Science and Technology, China) Sen Song (Tsinghua University, China) Tutorial Chair Wenming Zheng (South East University, China) Publicity Chairs Tielin Zhang (Chinese Academy of Sciences, China) Shouyi Wang (University of Texas at Arlington, USA) Yang Yang (Maebashi Institute of Technology, Japan, and Beijing Advanced Innovation Center for Future Internet Technology, Beijing University of Technology, China) Steering Committee Chairs Ning Zhong (Maebashi Institute of Technology, Japan) Hanchuan Peng (Allen Institute for Brain Science, USA) *** Contact Information *** tielin.zhang(a)ia.ac.cn shouyiw(a)uta.edu yang(a)maebashi-it.org

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CFP: Special Issue on 'Software Defined Networking and Network Function Virtualization' in Scalable Computing and Communications (Springer)
by Javid Taheri 14 Aug '17

14 Aug '17

--------------------------------------------------------------------------------- Please accept our apologies if you receive multiple copies of this CFP --------------------------------------------------------------------------------- CALL FOR PAPERS Scalable Computing and Communications ~Special Issue Call for Papers~ Software Defined Networking and Network Function Virtualization IMPORTANT DATES: - Submission Deadline: 15 Dec 2017 - Notification of Acceptance: 31 March 2018 - Final Version: 31 May 2018 INTRODUCTION AND MOTIVATION With maturity of virtualization techniques, more and more services are to be run inside virtualized Data Centers vDCs) to further reduce Operational (OPEX) and Capital Expenditures (CAPEX). Aligned with the general trend of migrating traditional IT architectures to clouds (public or private), next generation of telecommunication networks such as 5G are also envisaged to be run on virtualized environments where network functions are deployed on virtual machines and/or containers instead of current proprietary equipment. Several proof-of-concept and initial industrial deployments proved that Software Defined Networking (SDN) and Network Function Virtualization (NFV) are two promising technologies to enable such technological shift. Nevertheless, how to optimize and guarantee the performance of such virtualized systems is still challenging, because they require accurate modelling and efficient optimization to satisfy ever increasing demand of future networks. To address several major issues raised by migrating network applications to virtualized infrastructures, this special issue aims to highlight challenges, state-of-the-art, and solutions to a set of currently unresolved key questions including, but not limited to: performance, modelling, optimizations, reliability, security, and techno-economic aspects of virtualized networks. By addressing these concerns, technology might be one step closer to understanding, and consequently, closing the gap between the performance of the next generation SDN/NFV-based networks and their current counterparts in proprietary boxes. In this special issue, we welcome contributions that can shed light onto any of the following questions: 1. How virtualized networks should be designed to guarantee the performance required by network operations? 2. How virtualized services can be benchmarked and/or compared? 3. How virtualized services should be designed and/or operated to take advantage of cloud infrastructures and further provide flexibilities (such as load migration) that current proprietary equipment cannot provide? 4. How network functions should be placed and/or network capacities should be sliced to optimize network critical metrics such as throughput, delay, jitter, etc.? 5. How virtualized services should/can be efficiently orchestrated, monitored, and managed? PAPER SUBMISSION: - Authors are encouraged to submit high-quality, original work that has neither appeared in, nor is under consideration by, other journals. - All papers will be reviewed following standard reviewing procedures for the Journal. - Papers must be prepared in accordance with the Journal guidelines: www.springer.com/41122 - Submit manuscripts to: http://SCAC.edmgr.com. Topics to be covered in this Special Issue are including, but not limited to: 1. Model, benchmark, and/or optimize operation of SDN/NFV-based networks and services. 2. Resource and/or content allocation for SDN/NFV-based networks and services. 3. Reliability and resiliency of SDN/NFV-based networks and services. 4. Dynamic/flexible construction and deployment of Service Function Chains using SDN/NFV technologies. 5. Fault detection and/or correction for SDN/NFV-based networks and services. 6. Architectures, applications, and use cases of SDN/NFV to provide networking services. 7. Monitoring techniques for SDN/NFV-based networks and services. 8. Deployment, management, and orchestration of SDN/NFV-based networks and services. 9. Business/economic aspects of SDN/NFV-based networks and services. 10. Security concerns of SDN/NFV-based networks and services. 11. Mobile and/or Wireless Networks enabled by SDN/NFV-based networks and services.

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