Dear Colleague,
We invite you to submit a contribution to SPIFEC 2017, the 1st European
Workshop on Security and Privacy in Fog and Edge Computing. The paper
submission deadline is June 30th.
This workshop will be held on September 14th, in conjunction with
ESORICS 2017. Revised accepted papers will be published as a joint
post-proceedings by Springer in the Lecture Notes in Computer Science
(LNCS) series with other ESORICS Workshops. More information is
available at: https://www.nics.uma.es/pub/spifec
Looking forward to meeting you in Oslo! Best regards, the organizers,
Rodrigo Roman, Chunming Rong, Ruben Rios
Apologies if you receive multiple copies of this email!
________________________________
********** WORKS 2017 Workshop **********
Workflows in Support of Large-Scale Science Workshop
http://works.cs.cardiff.ac.uk/
Monday 13 November 2017, Denver, Colorado, USA.
Held in conjunction with SC17, http://sc17.supercomputing.org/
Paper submission deadline: 30 July 2017
*****************************************
Call For Papers
Data-intensive workflows (a.k.a. scientific workflows) are routinely used
in most scientific disciplines today, especially in the context of
high-performance, parallel and distributed computing. They provide a
systematic way of describing a complex scientific process and rely on
sophisticated workflow management systems to execute on a variety of
parallel and distributed resources. With the dramatic increase of raw data
volume in every domain, they play an even more critical role to assist
scientists in organizing and processing their data and to leverage HPC or
HTC resources, being at the interface between end-users and computing
infrastructures.
This workshop focuses on the many facets of data-intensive workflow
management systems, ranging from actual execution to service management
and the coordination and optimization of data, service and job
dependencies. The workshop covers a broad range of issues in the
scientific workflow lifecycle that include: data-intensive workflows
representation and enactment; designing workflow composition interfaces;
workflow mapping techniques to optimize the execution of the workflow for
different infrastructures; workflow enactment engines that need to deal
with failures in the application and execution environment; and a number
of computer science problems related to scientific workflows such as
semantic technologies, compiler methods, scheduling and fault detection
and tolerance.
The topics of the workshop include but are not limited to:
Big Data analytics workflows
Data-driven workflow processing (including stream-based workflows)
Workflow composition, tools, and languages
Workflow execution in distributed environments (including HPC,
clouds, and grids)
Reproducible computational research using workflows
Dynamic data dependent workflow systems solutions
Exascale computing with workflows
Workflow fault-tolerance and recovery techniques
Workflow user environments, including portals
Workflow applications and their requirements
Adaptive workflows
Workflow optimizations (including scheduling and energy efficiency)
Performance analysis of workflows
Workflow debugging
Workflow provenance
Interactive workflows (including workflow steering)
*****************************************
Important Dates
Papers Due: 30 July 2017
Notifications of Acceptance: 9 September 2017
E-copyright registration completed by authors: 1 October 2017
Final Papers Due: 1 October 2017
Submitted papers must be at most 10 pages long. The proceedings should be
formatted according to
http://www.acm.org/publications/proceedings-template. WORKS papers will be
published in collaboration with SIGHPC and will be available from both ACM
and IEEE digital repositories.
*****************************************
WORKS 2017 Organizing Committee
– PC Chairs
Sandra Gesing, University of Notre Dame, USA
Rizos Sakellariou, University of Manchester, UK
– General Chairs
Johan Montagnat, CNRS, Sophia Antipolis, France
Ian Taylor, Cardiff University, UK and University of Notre Dame, USA
– Steering Committee
David Abramson, University of Queensland, Australia
Malcolm Atkinson, University of Edinburgh, UK
Ewa Deelman, University of Southern California, USA
Michela Taufer, University of Delaware, USA
– Publicity Chairs
Rafael Ferreira da Silva, USC, USA
Ilia Pietri, University of Athens, Greece
*****************************************
WORKS 2017 Program Committee
Pinar Alper, King's College London, UK
Ilkay Altintas, San Diego Supercomputer Center, USA
Khalid Belhajjame, Université Paris-Dauphine, France
Adam Belloum, University of Amsterdam, the Netherlands
Ivona Brandic, TU Wien, Austria
Kris Bubendorfer, Victoria University of Wellington, New Zealand
Jesus Carretero, Universidad Carlos III de Madrid, Spain
Henri Casanova, University of Hawaii at Manoa, USA
Ewa Deelman, USC Information Sciences Institute, USA
Rafael Ferreira Da Silva, USC Information Sciences Institute, USA
Daniel Garijo, USC Information Sciences Institute, USA
Sandra Gesing, University of Notre Dame, USA
Tristan Glatard, CNRS, France
Daniel Katz, University of Illinois Urbana-Champaign, USA
Tamas Kiss, University of Westminster, UK
Dagmar Krefting, HTW Berlin, Germany
Maciej Malawski, AGH University of Science and Technology, Poland
Anirban Mandal, Renaissance Computing Institute, USA
Marta Mattoso, Federal Univ. Rio de Janeiro, Brazil
Andrew Stephen Mcgough, Newcastle University, UK
Paolo Missier, Newcastle University, UK
Jarek Nabrzyski, University of Notre Dame, USA
Daniel de Oliveira, Fluminense Federal University, Brazil
Ilia Pietri, University of Athens, Greece
Radu Prodan, University of Innsbruck, Austria
Omer Rana, Cardiff University, UK
Ivan Rodero, Rutgers University, USA
Rizos Sakellariou, University of Manchester, UK
Domenico Talia, University of Calabria, Italy
Rafael Tolosana-Calasanz, Universidad de Zaragoza, Spain
Chase Wu, New Jersey Institute of Technology, USA
Call for Papers: International Conference on Embedded and VLSI Design 2018
-------------------------------------------------------------------------
The 31st International Conference on VLSI Design
The 17th International Conference on Embedded Systems
January 6-11, 2018, Pune, India
http://embeddedandvlsidesignconference.org
This joint conference is a forum for researchers and designers to present
and discuss current topics in VLSI design, electronic design automation,
embedded systems, and emerging technologies. Two days of tutorials will be
followed by three days of regular paper sessions, special sessions, and
embedded tutorials. Industry presentation sessions along with exhibits,
panel discussions, Design Contest, and Education Forum round off the
program. The conference is followed by the Reliability Aware System Design
and Test (RASDAT) workshop.
TOPICS OF INTEREST: Papers are invited on previously unpublished results in
the following categories:
********************************
EMBEDDED SYSTEMS DESIGN
E1: Embedded Systems Hardware:
HW/SW co-design, SoC, multi-core
systems, board level hardware, HW security, Internet-of-Things (IoT)
devices, sensors/actuators, displays
E2: Embedded Systems Software:
Operating systems, firmware, algorithms, middleware, runtimes,
parallelization, virtualization, software for low power, security,
reliability, real-time support, emerging applications (e.g., automotive,
telematics, analytics)
E3: FPGA and Reconfigurable Systems: FPGA architecture and FPGA
circuit design, CAD for FPGA, FPGA prototyping, FPGA-based accelerators
E4: Wireless Systems: Sensor networks, low-power wireless systems, wireless
protocols, wireless power delivery
E5: Embedded Case Studies: Practical and industrial tools, methodologies,
designs in various application areas: wireless, medical, networking,
multimedia, automotive, controls, etc.
DESIGN TOOLS AND EDA
T1: Design Verification: Functional, formal, coverage-driven,
hardware-assisted, and assertion-based verification, behavioral, RTL, and
gate-level simulation, emulation, equivalence checking
T2: Test, Reliability, Fault-Tolerance:
DFT, fault modelling and simulation, ATPG, BIST, repair, delay test, fault
tolerance, online test, AIMS/RF test, board-level and system-level test,
silicon debug, post-silicon validation, memory test, reliability testing
T3: Computer-Aided Design (CAD): Logic and behavioral synthesis, logic
mapping, simulation and formal verification, layout (partitioning,
placement, routing, floor planning, and compaction), post route
optimizations
DESIGN METHODOLOGIES AND TECHNOLOGY
M1: System-level Design: Methodologies and architectures, processor and
memory design, multi-core, GPU design, networks-on-chip, defect-tolerant
architectures, accelerators, distributed systems (e.g., automotive),
cyber-physical systems
M2: Advances in Digital Design: Logic and physical synthesis, place and
route, clock tree design, timing and signal integrity, design for
manufacturability and yield, power integrity, variation-tolerant design
M3: Analog, Mixed-Signal, and RF Design: Design of analog, mixed signal,
and RF IP, high-speed wired and wireless interfaces, low-power analog and RF
M4: Power-Aware Design: Power analysis and estimation, optimization and
low-power design, energy-efficient design, battery-aware design, thermal
management, energy harvesting
M5: CMOS Technology and Devices: Deep nanoscale CMOS devices, device
modelling and simulation, multi-domain simulation, device/circuit-level
reliability and variability
M6: Emerging Technologies: Post-CMOS devices, MEMS sensors, biomedical
circuits, lab-on-chip, carbon nanotubes, silicon photonics, spintronic,
memristors, neuromorphic and quantum computing
SAFE AND SECURE INTELLIGENT SYSTEMS
S1: Design for Safety and Reliability
Physically unclonable functions, random number generators, fault tolerance
systems and architectures
S2: Secure Circuits and Systems
System security, side channel attacks and anti-piracy methodologies,
Embedded systems security in healthcare, automotive, industrial and IoT
applications
S3: Safety Assurance of Circuits/ Systems
Design for functional safety and certifications in airborne, health care,
automotive systems
********************************
EMBEDDED TUTORIALS AND SPECIAL SESSIONS: Proposals in relevant emerging
areas should be submitted as two-page abstracts. On acceptance, authors are
required to submit full regular papers.
HALF-DAY AND FULL-DAY TUTORIALS: Tutorial proposal are invited for topics
of interest including VLSI design, EDA, VLSI technology, and embedded
systems. The tutorials will be arranged on the first two days of the
conference.
PANELS: Proposals must be submitted with an abstract, and a list of
panelists.
SUBMISSIONS: All submissions should be made electronically via the
conference website by July 16, 2017. Your manuscript should clearly state
the novel ideas, results, and applications of the contribution. Paper
submissions will undergo a double-blind review. Papers must be in PDF
format and not exceed 6 single-spaced pages including figures and
references in two-column IEEE conference paper format. Papers exceeding the
page limit or identifying the authors will be rejected without review.
EXHIBITS: Please contact the Exhibits Chair to explore opportunities to
display your products/services.
FELLOWSHIPS: The conference will award fellowships, based on need and
merit, to partially cover expenses of attendees from India. Application
details will be posted at the conference website.
DESIGN CONTEST: Please check the conference website or contact the Design
Contest Chair for more details.
USER TRACK AND PHD FORUM: Please check the conference website for details
on criteria and submission dates.
IMPORTANT DATES:
Submission of Full paper deadline: July 16, 2017
Acceptance notification: September 17, 2017
Camera ready paper due: October 8, 2017
Call for Papers
The Third International Workshop on Security in NFV-SDN in conjunction with the 3rd IEEE NFV-SDN conference, 6-8 November, Berlin, Germany
Workshop website: http://www.sn-2017.info/
Scope
Network Function Virtualization (NFV) and Software Defined Network (SDN) have changed the networking industry dramatically. NFV virtualizes network services by utilizing virtualization technologies to reduce the dependency on underlying hardware. NFV provides many benefits such as faster service enablement, ease of resource management and lower OPEX and CAPEX. SDN separates the control functions from the underlying physical network by decoupling the control and data planes. SDN provides many benefits such as reduced costs, ease of deployment and management, better scalability, availability, flexibility and fine-grain control of traffic and security. Like traditional networks, they are subject to various security threats and attacks. In this workshop, we invite high-quality submissions in the areas of NFV and SDN security and other related areas. Submitted papers should highlight methods and approaches that can be used to analyse the security risks and requirements, threats and techniques related to NFV and SDN and to provide novel methods and approaches to assure security in NFV and SDN.
Topics of interest
Topics of interest include but are not limited to the following areas:
· Security, reliability and privacy through SDN and NFV in 5G networks
· Management and orchestration of NFV and SDN elements for security
· Secure design of NFV and SDN solutions, security enablers
· Security threats and vulnerabilities introduced by NFV and SDN technologies
· Threat detection and mitigation through SDN and NFV
· Security policy specification and management in SDN and NFV systems
· Security related monitoring and analytics in SDN and NFV solutions
· 5G security architecture, trust and confidence
· Authentication, authorization and Accounting in SDN
· Security of applying SDN to wireless and mobile network
· Security of applying NFV and SDN to IoT
· Security of applying NFV and SDN to cloud computing
· Security of SDN API
· Risk and compliance issues in SDN
· Securing SDN infrastructure
· Security architecture for SDN
· Security standard of SDN
· Security of SDN data plane
· Security of SDN control plane
· Security of SDN application plane
· Security of Routing in SDN
· Security of network slicing
· Security as a service for SDN
The workshop deadlines:
· Paper Submission: June 30, 2017
· Notification of Acceptance: July 15, 2017
· Camera Ready Submission: September 15, 2017
Submission
Please use EDAS to upload your submission at http://edas.info/N23798. The manuscripts must be prepared in English, following IEEE two‐column Manuscript Templates (http://www.ieee.org/conferences_events/conferences/publishing/templates.html) for Conference Proceedings with a maximum length of six (6) printed pages for full papers and up to four (4) pages for short papers (work in progress), including figures. All papers need to be submitted in PDF format via EDAS<http://edas.info/N23798>. All submitted papers will be peer‐reviewed. To be published in the Workshop Proceedings and to be eligible for publication in IEEE Xplore, at least one author of an accepted paper is required to register and present the paper at the workshop. The IEEE reserves the right to exclude a paper from distribution after the conference (including its removal from IEEE Explore) if the paper is not presented at the conference. Papers are reviewed on the basis that they do not contain plagiarized material and have not been submitted to any other conference at the same time (double submission). These matters are taken very seriously and the IEEE Communications Society will take action against any author who engages in either practice.
Workshop Chairs
· Eleni Trouva, NCSR Demokritos, Greece
· Shao Ying Zhu, University of Derby,UK
· George Gardikis, Space Hellas, Greece
· Collin Allison, University of St Andrews,UK
· Linas Maknavicius, Nokia Bell Labs, France
Technical Program Committee (TPC)
· Diego Lopez – Telefonica I&D, Spain
· Harilaos Koumaras – NCSR Demokritos, Greece
· Muhammad Shuaib Siddiqui – i2CAT, Spain
· Ludovic Jacquin – Hewlett Packard Labs, UK
· Nicolae Paladi, Swedish Institute of Computer Science, Sweden
· Augusto Ciuffoletti – University of Pisa, Italy
· Carolina Canales – Ericsson, Spain
· Michail-Alexandros Kourtis – NCSR Demokritos, Greece
· Marco Anisetti – University of Milan, ItalyMarco Anisetti – University of Milan, Italy
· Sandra Scott-Hayward – Queen’s University Belfast, UK
· Miguel Angel Garcia – Ericsson, Spain
· Antonios Litke – Infili, Greece
· Nikolaos Papadakis – Infili, Greece
· Dimitris Katsianis, Incites, Luxemburg
· Antonio Agustin Partor Perales – Telefonica I&D, Spain
· Yacine Rebahi, Fraunhofer Institute for Open Communication Systems FOKUS, Germany
· Abdelkader Outtagarts – Nokia, Bell Labs, France
Contacts
Eleni Trouva - trouva(a)iit.demokritos.gr<mailto:trouva@iit.demokritos.gr>
Dr. Shao Ying Zhu - s.y.zhu(a)derby.ac.uk<mailto:s.y.zhu@derby.ac.uk>
Dr. George Gardikis - ggar(a)space.gr<mailto:ggar@space.gr>
Linas Maknavicius - linas.maknavicius(a)nokia-bell-labs.com<mailto:linas.maknavicius@nokia-bell-labs.com>
Dr. Colin Allison - ca(a)st-andrews.ac.uk<mailto:ca@st-andrews.ac.uk>
The University of Derby has a published policy regarding email and reserves the right to monitor email traffic.
If you believe this was sent to you in error, please reply to the sender and let them know.
Key University contacts: http://www.derby.ac.uk/its/contacts/
Apologies if you receive multiple copies of this email!
________________________________
********** WORKS 2017 Workshop **********
Workflows in Support of Large-Scale Science Workshop
http://works.cs.cardiff.ac.uk/
Monday 13 November 2017, Denver, Colorado, USA.
Held in conjunction with SC17, http://sc17.supercomputing.org/
Paper submission deadline: 30 July 2017
*****************************************
Call For Papers
Data-intensive workflows (a.k.a. scientific workflows) are routinely used
in most scientific disciplines today, especially in the context of
high-performance, parallel and distributed computing. They provide a
systematic way of describing a complex scientific process and rely on
sophisticated workflow management systems to execute on a variety of
parallel and distributed resources. With the dramatic increase of raw data
volume in every domain, they play an even more critical role to assist
scientists in organizing and processing their data and to leverage HPC or
HTC resources, being at the interface between end-users and computing
infrastructures.
This workshop focuses on the many facets of data-intensive workflow
management systems, ranging from actual execution to service management and
the coordination and optimization of data, service and job dependencies.
The workshop covers a broad range of issues in the scientific workflow
lifecycle that include: data-intensive workflows representation and
enactment; designing workflow composition interfaces; workflow mapping
techniques to optimize the execution of the workflow for different
infrastructures; workflow enactment engines that need to deal with failures
in the application and execution environment; and a number of computer
science problems related to scientific workflows such as semantic
technologies, compiler methods, scheduling and fault detection and
tolerance.
The topics of the workshop include but are not limited to:
Big Data analytics workflows
Data-driven workflow processing (including stream-based workflows)
Workflow composition, tools, and languages
Workflow execution in distributed environments (including HPC,
clouds, and grids)
Reproducible computational research using workflows
Dynamic data dependent workflow systems solutions
Exascale computing with workflows
Workflow fault-tolerance and recovery techniques
Workflow user environments, including portals
Workflow applications
Third IEEE Workshop on
Quantum Communications and Information Technology (QCIT’17)
-----------------------------------------------------------
http://qcit.committees.comsoc.org/qcit17-workshop/
At IEEE Globecom’17, Singapore, 4-8 December 2017
http://globecom2017.ieee-globecom.org
The scope of this dedicated workshop is to explore the opportunities for
application of communications theory and technologies to quantum
technology
and its applications. The workshop is the annual main event of ComSoc’s
Emerging Technical Committee on Quantum Communications and Information
Technology (ETC-QCIT).
Over the last decade, a wide variety of experimental quantum
communications
and processing devices has been invented and used for fundamental
demonstrations in laboratories. Results confirm feasibility of real
applications in quantum communications and information related fields.
Recently one can observe upcoming applications in areas like a quantum
communications, quantum sensors and random number generators which are
partially even commercially available. Companies and governments started
to
spend significant amounts of funding in research and development of
quantum
technologies. However, the step from quantum technology based devices to
real systems running a communications or information processing task has
not
completed yet. Moreover, many problems show opportunities to contribute
with
knowhow, technologies and engineering out of the communications area. The
following topics are crucial to the development of future quantum
technology
based systems:
- Algorithms and applications complexity
- Analysis of classical vs quantum software
- Coding theory
- Coherent routers, repeaters and converters
- Communications and information theory
- Devices and circuits
- Entanglement distillation
- Error correction
- Experimental results and demonstrations
- Interconnection and complexity theory
- Metrology for quantum systems
- Modeling and simulation
- Network coding
- Photonic communications technology
- Processing and systems architecture
- Quantum electro-dynamics
- Quantum information theory
- Quantum key distribution
- Quantum sensors
- Quantum-algorithms and applications
- Remote state preparation
- RF based programming and algorithms
- RF technology and control
- Signal processing for quantum control
It is the aim of this workshop to connect people from academia and
industry
to discuss about theory, technology and applications and exchange ideas to
move efficiently forward in research, engineering and development of this
exciting area.
Submission info for camera-ready manuscripts
--------------------------------------------
Original and unpublished regular papers are solicited from the
above-mentioned
areas. Regular papers have a length of 4 to 6 pages with an optional
payable
7th page. All manuscripts will be peer reviewed and published in the
workshop
proceedings and after presentation in IEEE Xplore. Templates for the
manuscripts can be downloaded from:
http://www.ieee.org/conferences_events/conferences/publishing/templates.html
The formatted manuscript should be electronically submitted as pdf via
EDAS:
https://edas.info/newPaper.php?c=23835
Further information is available in the Globecom 2017 webpages:
http://globecom2017.ieee-globecom.org
Important dates
---------------
Manuscript submission due date: 1. July, 2017
Notification date: 1. September, 2017
Final manuscript due date: 1. October, 2017
Conference date: 4.-8. December, 2017
Workshop organizers
-------------------
Andrea Conti, University of Ferrara, Italy, a.conti(a)ieee.org
Lajos Hanzo, University of Southampton, United Kingdom, lh(a)ecs.soton.ac.uk
Peter Mueller, IBM Research Zurich Laboratory, Switzerland,
pmu(a)zurich.ibm.com
Michael Ng, University of Southampton, United Kingdom, sxn(a)ecs.soton.ac.uk
Dear Colleagues,
We would like to invite you to submit your papers to the IEEE International
Workshop on Cyber-Physical Systems Security (CPS-Sec) to be held in
conjunction with the IEEE Conference on Communications and Network
Security (CNS), http://cns2017.ieee-cns.org/ in Las Vegas, NV USA,
October 9-11, 2017.
The CPS-Sec Workshop will primarily focus on the security and privacy
aspects of Cyber-Physical Systems and Internet of Things. The workshop will
include papers (both novel and work-in-progress submissions), invited
talks, panels, and discussions to facilitate the exchange of research ideas
in a community environment. We are sure that the CPS-Sec workshop will
greatly benefit from your contributions.
The submission deadline is July 18, 2017 and the author notification is
planned for August 9, 2017.
We look forward to your contributions. Please feel free to contact the TPC
Chairs of the CPS-Sec Workshop (suluagac(a)fiu.edu, conti(a)math.unipd.it,
kakkaya(a)fiu.edu) should you have any questions.
For more information regarding the workshop, please visit
http://cns2017.ieee-cns.org/workshop/cps-sec-international-workshop-cyber-
physical-systems-security
Thank you in advance.
----------------------------------
Nico Saputro
Department of Electrical and Computer Engineering
Florida International University
----------------------------------------------------------------------------------------
Please accept our apologies if you have received multiple copies.
-----------------------------------------------------------------------------------------
Deadline Extension
-------------------- REV-A 2017 CFP ---------------------
Re-Emergence of Vector Architectures Workshop - https://rev-a.github.io/
To be held in Conjunction with the IEEE Cluster 2017
September 5, 2017, Honolulu, Hawaii, USA
Paper submission: REV-A Submission<https://easychair.org/conferences/overview.cgi?a=13663824>
Papers due: June 25, 2017
The commoditization of high performance computing to a broader range of applications coupled with the reduction in performance improvement from traditional scaling technologies has led to a broad interest in a number of new compute acceleration technologies from GPGPUs to CGRAs and FPGAs. Meanwhile, SIMD widths have been widening to try to keep up with computational demand and general purpose architectures have started incorporating features from the vector architectures that used to dominate high performance computing. From IBM's Vector Media eXtension (VMX) to NEC's SX architecture to Intel's Advanced Vector eXtension (AVX) to ARM's recently announced Scalable Vector Extension (SVE) -- all of the major general purpose architectures seem to have embraced a return to vector based functionality.
Supporting these hardware developments there are a number of features being proposed for incorporation into modern programming models and languages in order to support the vector additions as well as restructuring memory access in order to feed the computational pipelines. Meanwhile application developers have been hard at work trying to refactor code to take advantage of wider vector units and more complicated memory hierarchies. Tools and techniques for developing for these new vector architectures are still evolving, particularly on emerging languages and runtimes.
The REV-A 2017 workshop will be a full-day meeting to be held at the IEEE Cluster 2017, in Honolulu, Hawaii, focusing on all aspects of vector architectures, programming models, programming frameworks, and applications. Topics of interest, of both theoretical and practical significance, include but are not limited to:
* Programming framework
* Programming model and language explorations
* Compilation and optimization including:
o algorithmic improvements
o code optimization
* Performance Analysis and Debugging Tools
* Performance Metrics and Evaluations
* Libraries and run-time systems
* Design, generation, verification and validation of representative applications
* Case-studies of representative applications
* Innovative applications for vector architectures
* Hardware studies and micro-architectural implementation tradeoffs
The REV-A workshop proceedings will be published along with the IEEE Cluster Digital Library. Submitted manuscripts should follow the IEEE Xplore format for publication: not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages, including figures, tables, and references. Manuscripts must be submitted electronically in PDF format. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers may not have appeared in or be under consideration for another workshop, conference, or journal. Accepted papers will have a page limit of 8 pages, and authors can purchase an additional 2 pages, for a total of 10 pages maximum.
Important Dates:
Papers due: June 25, 2017 <<<--- Extension
Author notification: July 17, 2017
Camera-ready final papers due: July 30, 2017
REV-A Workshop: September 05, 2017
Workshop Chairs:
Luiz DeRose Cray Inc.
Eric Van Hensbergen ARM Research
Program Committee:
David Abramson University of Queensland
Bronis R. de Supinski Lawrence Livermore National Laboratory
Mootaz N. Elnozahy KAUST
Roger Espasa SemiDynamics
Michael Garland NVIDIA
Ian Karlin Lawrence Livermore National Laboratory
David Lilja University of Minnesota
Sally McKee Chalmers University of Technology
Sanyam Mehta Cray Inc.
Hiroshi Nakashima Kyoto University
Lawrence Rauchwerger Texas A&M University
Mitsuhisa Sato Riken
Sunil Shrestha Cray Inc.
Xinmin Tian Intel
Mateo Valero Barcelona Supercomputing Center / UPC
Jeffrey Vetter Oak Ridge National Laboratory
Felix Wolf TU Darmstadt
Pen-Chung Yew University of Minnesota
[Our apologies if you receive multiple copies of this CFP]
------------------------------------------------------------------------------------------------------------------------------------
Call-for-Papers
The 2nd IEEE Cyber Science and Technology Congress (CyberSciTech 2017)
http://cyber-science.org/2017/
Orlando, USA, 6-10 November 2017
Sponsored by IEEE Computer Society and IEEE Technical Committee of Scalable
Computing (TCSC)
INTRODUCTION
---------------------
The modern digitized world has led to the emergence of a new paradigm on
global information networks and infrastructures known as Cyberspace and the
studies of Cybernetics, which bring seamless integration of physical,
social and mental spaces. Cyberspace is becoming an integral part of our
daily life from learning and entertainment to business and cultural
activities. As expected, this whole concept of Cybernetics brings new
challenges that need to be tackled.
To address these emerging challenges, there is a need to establish new
science and research portfolios that incorporate cyber-physical,
cyber-social and cyber-mental technologies together in a coherent manner to
deliver the vision of Cyberspace. This is the aim of the 2017 IEEE Cyber
Science and Technology Congress (CyberSciTech 2017) to offer a common
platform for scientists, researchers and engineers to share their latest
ideas and to exchange the latest developments and outcomes in their
research and technologies, with a broad scope of cyber-related science,
technology and application topics. CyberSciTech 2017 covers four main
research tracks including but not limited the following areas or topics.
IMPORTANT DATES
--------------------------
Paper Submission Due: July
10, 2017
Authors Notification: August
10, 2017
Camera-Ready Manuscript Due: September 1, 2017
SCOPE AND TOPICS
--------------------------
CyberSciTech 2017 covers four main research tracks including but not
limited the following areas or topics.
Track 1: Cyber Science and Fundamentals
Cyberspace Structure & Property, Cyber-world Constituents & Evolution,
Cyberspace & Cyber-world Modeling, Cyber-enabled Hyper-connection, Cyber
Visualization, Web Science, Internet Science, Data Science, Cyber Physical
Science, Cyber Social Science, Cyber Human Science, Cyber Life Science,
Cyber Physics, Cyber Biology, Cyber Ecology, Cyber Dynamics, Cyber Security
Track 2: Cyber Physical Computing and Systems
Cyber-Physical Systems, Cyber-Physical Interface, Cyber-Physical Hybrid
Intelligence, Ambient Intelligence, Intelligent Transportation Systems,
Networked Robots, Virtual Reality, Augmented Reality, Wearable/Bearable
Computing, Cyborg, Internet of Things (IoT), Smart Object, Smart Sensor,
Smart Environment, Smart City, Smart Agriculture, Smart Manufacture, Smart
Healthcare, Smart Service, Smart Cloud, Smart World
Track 3: Cyber Social Networks and Computing
Cyber-Social Networks, Cyber-Sociology, Cyber-Culture, Cyber-Economy,
Cyber-Social Evolution, Cyber-Social Sensing, Cyber-Social Simulation,
Cyber-Behavior Analytics, Cyber-Crowdsourcing, Cyber-Trust, Cyber-Privacy,
Cyber-Rights, Cyber-Crime, Cyber-Law, Cyber-Telepathy, Anticipatory
Computing
Track 4: Cyber Mind and Mental Computing
Cyber-Brain, Cyber-Individual, Cyber-Life, Cyber/Digital Clone, Cyber-Human
Evolution, Cyber-Psychology, Cyber-Cognition, Cyber-Affordance, Cyber-Human
Analytics, Cyber-based Learning, Cyber-Thinking, Cyber-Creation, Affective
Computing, Emotional Computing, Mental Computing, Sentiment Analysis
SUBMISSION GUIDELINES
----------------------------------
Authors are invited to submit their original work that has not previously
been submitted or published in any other venue. Submitted papers need to
abide by IEEE Computer Society formats. Final papers must be formatted
accordingly (see “IEEE Manuscript Templates
<http://www.ieee.org/conferences_events/conferences/publishing/templates.html>”)
and submitted via EDAS https://edas.info/newPaper.php?c=23118.
Proposals for organizing tutorials, workshops and special sessions need to
be submitted to the Tutorials, Workshops and Special Sessions Chairs,
respectively by emailing cyberscitechcongress(a)gmail.com. A proposal should
include title, theme, scope and main presenters/organizers.
Main track, workshop/special session, poster (short) papers all need to be
in IEEE CS format and submitted following the same instruction on the
CyberSciTech 2017 congress web site. A main track, workshop, or special
session paper should be between 6-8 pages. A poster (short) paper should be
between 2-4 pages.
All accepted papers in the main tracks, workshops, special sessions and
demos/posters will be published in an IEEE Computer Society proceedings (EI
indexed). Extended versions of selected excellent papers will be considered
for publication in special issues of the following journals. ((
http://cyber-science.org/2017/si.html).
1 - IEEE Cloud Computing (https://www.computer.org/cloud-computing)
2 – Scalable Computing and Communications - Special Issue on "Scalable
Algorithms and Behavior Analytics in Cyber-Enabled World" (
http://www.springer.com/?SGWID=0-102-2-1572358-preview&dynamic=true)
3 - Future Generation Computer Systems (
https://www.journals.elsevier.com/future-generation-computer-systems)
4 - Elsevier Ad Hoc Networks (
https://www.journals.elsevier.com/ad-hoc-networks)
Please distribute widely and accept our apologies for cross-posting *
***************
CALL FOR PAPERS
***************
(Extended version: June 26th, 2017)
*** Extended versions of selected papers will be published in Journal of Intelligent Information Systems, published by Springer ***
The 9th International ACM Conference on Management of Digital EcoSystems (MEDES'17)
In-Cooperation with ACM, ACM SIGAPP and IFIP WG 2.6
http://sigappfr.acm.org/MEDES/17/
November 7-10, 2017
Bangkok, Thailand
Description and Objectives
---------------------------
In the world of the Internet of Things (IoT), the rapid growth and exponential use of digital components leads to the emergence of intelligent environments namely "digital ecosystems" connected to the web and composed of multiple and independent entities such as individuals, organizations, services, software and applications sharing one or several missions and focusing on the interactions and inter-relationships among them. With the help of the computational intelligence, these digital ecosystems can exhibit new self-* properties (such as self-management, self-healing and self-configuration) environments, thanks to the re-combination and evolution of its "digital components", in which resources provided by each entity are properly conserved, managed and used. The underlying web-based resources mainly comprehend big data management, innovative services, smart and self-* properties platforms.
Due to the multi-disciplinary nature of digital ecosystems, they are highly complex to study and design. This also leads to a poor understanding as to how managing resources will empower digital ecosystems to be innovative, intelligent and value-creating. The application of Information Technologies has the potential to enable the understanding of how entities request resources and ultimately interact to create benefits and added-values, impacting business practices and knowledge. These technologies can be improved through novel techniques, models and methodologies for fields such as big data management, web technologies, networking, security, human-computer interactions, artificial intelligence, e-services and self-organizing systems to support the establishment of digital ecosystems and manage their resources.
The International Conference on Management of Digital EcoSystems (MEDES),previously named "The International Conference on Management of Emergent Digital EcoSystems", aims to develop and bring together a diverse community from academia, research laboratories and industry interested in exploring the manifold challenges and issues related to resource management of Digital Ecosystems and how current approaches and technologies can be evolved and adapted to this end.
MEDES 2017 calls for full papers presenting interesting recent results or novel ideas in all areas of Emergent Digital EcoSystems. At the same time, the conference calls for short papers presenting interesting and exciting recent results or novel thought-provoking ideas that are not quite ready, and preferably include a system demonstration.
Topics
-------
MEDES 2017 seeks contributions in the following areas:
- Digital Ecosystem Infrastructure
- Data & Knowledge Management
- Computational and Collective Intelligence
- Semantic Computing
- Software ecosystems for software engineering
- Big Data
- Services
- Trust, Security & Privacy
- Software Engineering
- Internet of Things and Intelligent Web
- Cyber Physical Systems
- Social and Collaborative Platforms
- Human-Computer Interaction
- Open Source
- Applications (Logistics, Energy, Healthcare, Environment, Smart Cities, Digital Humanities, Robotics, etc.)
- Complex Systems and Networks
Paper Submission
----------------
Submissions must be in an electronic form as PDF format and should be uploaded using the conference website. The submitted paper should be at most 8 ACM single-space printed pages. Papers that fail to comply with length limit will be rejected.
Submissions will be peer-reviewed by at least 3 peer reviewers. After the preliminary notification date, authors rebut by evidence and arguments all reviewer inquiries and their comments. Based on the rebuttal feedback, reviewers notify authors with the final decision. Selection criteria will include: relevance, significance, impact, originality, technical soundness, and quality of presentation. Preference will be given to submissions that take strong or challenging positions on important emergent topics related to Digital Ecosystems. At least one author should attend the conference to present the paper.
The conference Proceedings will be published by ACM and indexed by the ACM Digital Library and DBLP.
Important Dates
----------------
- Submission Deadline: June 26th, 2017
- Notification of Acceptance: July 25th, 2017
- Camera Ready: September 1st, 2017
- Paper Registration: September 1st, 2017
- Conference Dates: 7-10 November 2017
Advisory Chairs
----------------
Yannis Manolopoulos, Aristotle University of Thessaloniki, Greece
Ernesto Damiani, Universita' degli Studi di Milano, Italy
Conference Chairs
----------------
Richard Chbeir, University of Pau and Adour Countries, France
Asanee Kawtrakul, Kasetsart University, Thailand
Program Chairs
----------------
William Grosky, University of Michigan-Dearborn, USA
Toshikazu Kato, Chuo University, Tokyo, Japan
Ali Ouni, Osaka University, Osaka, Japan
International Program Committee
--------------------------------
(Please check the web site for the full list)